Hello!
I'm working with the board based on DM8168 DVR ES 2.1 which, according to specs, has revision r3p2 of ARM Cortex-A8.
Recently I've tried OProfile's operf as well as perf utilities for performance profiling. During profiling results analysis I' found several articles (particularly, http://processors.wiki.ti.com/index.php/Oprofile_User's_Guide and http://ssvb.github.io/2011/08/23/yet-another-oprofile-tutorial.html) stating that ARM Cortex-A8 performance monitoring unit is broken and the using of timer interrupts is the only reliable profiling method with OProfile. It is noteworthy that neither of the articles I've found refer concrete A8 revisions where the issue is observed and I was not able to find is there any A8 revision where the issue is fixed.
Here is the issue description got from Freescale i.MX board errata (http://www.freescale.com/files/32bit/doc/errata/IMX50CE.pdf):
ARM #628216: Potential OVFL status loss when it occurs at CP15
and CP14 update
Description:
If the PMU is in use and an overflow event occurs simultaneously with a write to one of the subsets
of CP15 and CP14 registers, the overflow event can be lost.
The conditions are as follows:
1. The performance counters must be in use
2. The performance counter must have an overflow (counter value goes beyond 0xFFFF_FFFF)
3. Simultaneous with the counter overflow, a MCR instruction must be executed that writes to one
of the following CP14/CP15 registers:
— Any PMU register other than PMU counter registers
— ThumbEE Configuration Register
— ThumbEE Handler Base Register
— System Control Register
— Auxiliary Control Register
— Secure Configuration Register
— Secure Debug Enable Register
— Nonsecure Access Control Register
— Context ID and Thread ID Registers
— Coprocessor Access Register
— Cache Size Select Register
The issue is reported by ARM, erratum ID 628216, Category 2.
Projected Impact:
If the erratum occurs, the overflow status flag is not set for that counter in the Overflow Flag Status
Register, and an interrupt request is not generated, even when the Interrupt Enable Set Register is
configured to generate an interrupt on counter overflow.
Since the DM8168 board silicon errata (http://www.ti.com/lit/er/sprz329d/sprz329d.pdf) does not mention the issue I wonder whether ARM erratum #628216 affects my board or I can rely on profiling results obtained from measurements based on A8 hardware performance counters.
