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DM8168 decode resolution more than 1080p

colin he1
Intellectual 665 points


Hi, I have 2 question about DM1868 vdec capability.

One question is DM8168 can decode 2 channel 1920x1200 h264 bitstream?

And the othe question is DM1868 can decode 2 channel 1600x1200 h264 bitstream?

  • 0
    TI__Guru* 80190 points

    Hello,

    DM8168 Has 3xHDVICP.

    Each module is scalable in terms of resolutions and channels supported, so for example one HDVICP2 module at 533MHz could support 1x 1080p60 or 2x 1080p30 or 4x 720p30 or 10x SD h264 encodes/decodes.

    HDVPSS can handle maximum of 1920 pixels per line. Maximum pixel clock support for capture and display is upto 165MHz.
    From codec prospective, some of the codecs supports resolution upto 4kx4k. You could check this here(encoder/decoder user guides) for different decoder/encoders:

    /ti-ezsdk_dm816x-evm_5_05_02_00/component-sources/omx_05_02_00_48/src/ti/omx/docs

    The width is limited to 1920 pixels. This means 1920x1200@60 is fine (pixel clock < 165MHz)

    Best Regards,

    Margarita

  • 0 in reply to Margarita Gashova
    TI__Guru 59700 points

    colin he1 said:

    One question is DM8168 can decode 2 channel 1920x1200 h264 bitstream?

     
    It is possible to decode. What is the fps of the stream.
     
    colin he1 said:
     
    And the othe question is DM1868 can decode 2 channel 1600x1200 h264 bitstream?
     
     
    Yes decode of 2 channel 1600x1200 @ 60 fps is possible
  • 0 in reply to Badri Narayanan
    Prodigy 120 points

    HDVPSS can handle maximum of 1920 pixels per line. Maximum pixel clock support for capture and display is upto 165MHz.
    From codec prospective, some of the codecs supports resolution upto 4kx4k. You could check this here(encoder/decoder user guides) for different decoder/encoders:

     

    A little know fact is that a small FPGA fitted in front of each of HDVPSS Video Input ports and a bit of magic update to TI's CODEC will enable DM8168 to stream two (2) channels of SuperHD -  like 2560x1600 or 2048x2048 - @ 20FPS.

    The same principle could apply for even larger frames, effectively only limited by the number of slices the FPGA can divide into the limitation of the 165MHz sped of HDVPSS, but the Frame Rate will be reduced. Estimate is that 4096x4096 would stream at around 10 FPS for one channel. 

     



     

     

  • 0 in reply to Flemming_Sundance
    Guru 10685 points

    Hi Fleming, this sounds interesting: how can I get hold of this magic update to the codecs?

    Thanks,
    Ralph

  • 0 in reply to _Ralph_
    Prodigy 120 points

    http://www.ti.com/lit/ml/swpt054/swpt054.pdf - and it depends where you are in the World, but they should all have it available - at a cost!

    - and maybe one day TI will be kind and release it freely, as would instantly make DM81xx more attractive. They are still the best SoC for relative low-power H.264 compression and direct Video In/Out. I am sure TI will be pleased to hear

    Flemming

  • 0 in reply to Flemming_Sundance
    Guru 10685 points

    Thanks for the link. I agree, TI's chips are great hardware. It's just a shame the software support isn't better (or even existent!).