About codec engine of DM8168

feng xiao ming

HW：DM8168

SW：EZSDK

We can run codec engineer examples.But We must unload HDVPSS and HDVICP firmware first.How to enable the codec engineer while HDVPSS and HDVICP firmware is loaded? We need to use OMX component and codec engineer at the same time.

over 11 years ago

0 Margarita Gashova over 11 years ago

TI__Guru* 80190 points

Hello,

feng xiao ming said:
codec engineer

Are you mean Codec Engine?

Best Regards,

Margarita

0 _Ralph_ over 11 years ago in reply to Margarita Gashova

Guru 10685 points

Are you sure you have to unload the HDVPSS/HDVICP first? I have my system working with the HDVICP/HDVPSS loaded as well as using firmware_loader to run my algorithm on the DSP.

0 feng xiao ming over 11 years ago in reply to _Ralph_

Expert 1445 points

Margarita Gashova:

I mean the Codec Engine.

I sure I have to unload the HDVPSS/HDVICP first? You can see from the 'DM816x EZ Software Developers Guide'：

Note!The syslink samples use a different memory map from the default EZSDK installation. In order to run
syslink examples, you must boot with a different memory for linux. When booting, ensure that the linux
bootargs is changed from the default values toMEM=169M
Note!The Codec Engine examples cannot be run out with graphics. Please execute the following steps to
teardown the graphics plane and ensure that no firmware is running.

Dose there any method to make the HDVPSS/HDVICP and codec engine run at the same time.

0 _Ralph_ over 11 years ago in reply to feng xiao ming

Guru 10685 points

There is no hardware or software reason you cannot run both Codec Engine and HDVICP/HDVPSS at the same time.

What that text is saying is that you must have a coherent memory map between the different processors (DSP, ARM, HDVICP, HDVPSS) and to do this you need to check that the addresses programmed in are the same.

You can check the memory addresses match the DM8168 address map (see http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map) as follows:

-look in the firmware_loader source code and check the addresses there

-if you are using cmemk for memory sharing between DSP and ARM, make sure when you load the cmemk.ko module you have the correct arguments (i.e. addresses) passed to it

-check the source code of the Codec Engine examples to make sure the memory segments have the correct addresses

-check the kernel boot arguments and make sure the "mem=" arguments match those in the previously linked memory map.

You can search for more help on the forums using the term "memory map". This subject has already been covered quite well on here.

Ralph

0 Margarita Gashova over 11 years ago in reply to feng xiao ming

TI__Guru* 80190 points

Hello,

The reason for concurrency not working with CE (Codec Engine)examples and firmware binaries are due to the mismatch in memory map between Codec Engine examples and firmware binaries. Since Codec Engine supports multiple platforms, it has chosen a generic memory map, whereas firmware binaries use customized memory map optimized for OMX use cases. Please check the link

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map

for more details about EZSDK memory map.

If the memory map of CE example could be modified accordingly to the EZSDK memory map, then we can run both OMX use cases and CE examples concurrently.

Best Regards,

Margarita

0 feng xiao ming over 11 years ago in reply to Margarita Gashova

Expert 1445 points

hi, Margarita:

I have change the map as :

var TI816X_DSP_ExtMemMap = {
DDR3_HOST: {
comment: "DDR3 Memory reserved for use by the A8",
name: "DDR3_HOST",
base: 0x80000000,
len: 0x16C00000 /* 364 MB */
},
DDR3_DSP: {
comment: "DDR3 Memory reserved for use by the C674",
name: "DDR3_DSP",
base: 0x99500000,
len: 0x00C00000 /* 12 MB */
},
DDRALGHEAP: {
comment: "DDR3 Memory reserved for use by algorithms on the C674",
name: "DDRALGHEAP",
base: 0x98000000,
len: 0x01400000 /* 20 MB */
},
DDR3_SR1: {
comment: "DDR3 Memory reserved for use by SharedRegion 1",
name: "DDR3_SR1",
base: 0x99400000,
len: 0x00100000 /* 1 MB */
},
DDR3_HDVPSS: {
comment: "DDR3 Memory reserved for use by HDVPSS",
name: "DDR3_HDVPSS",
base: 0xBF900000,
len: 0x00200000 /* 2 MB */
},
DDR3_V4L2: {
comment: "DDR3 Memory reserved for use by V4L2",
name: "DDR3_V4L2",
base: 0xBFB00000,
len: 0x00200000 /* 2 MB */
},
DDR3_SR0: {
comment: "DDR3 Memory reserved for use by SharedRegion 0",
name: "DDR3_SR0",
base: 0x9F700000,
len: 0x00200000 /* 2 MB */
},
DDR3_M3: {
comment: "DDR3 Memory reserved for use by the M3 core",
name: "DDR3_M3",
base: 0x9D600000,
len: 0x00E00000 /* 16 MB */
},
};

var TI816X_VIDEOM3_ExtMemMap = {
DDR3_HOST: {
comment: "DDR3 Memory reserved for use by the A8",
name: "DDR3_HOST",
base: 0x80000000,
len: 0x16C00000 /* 364 MB */
},
DDR3_DSP: {
comment: "DDR3 Memory reserved for use by the C674",
name: "DDR3_DSP",
base: 0x99500000,
len: 0x00C00000 /* 12 MB */
},
DDR3_SR1: {
comment: "DDR3 Memory reserved for use by SharedRegion 1",
name: "DDR3_SR1",
base: 0x99400000,
len: 0x00100000 /* 1 MB */
},
DDR3_HDVPSS: {
comment: "DDR3 Memory reserved for use by HDVPSS",
name: "DDR3_HDVPSS",
base: 0xBF900000,
len: 0x00200000 /* 2 MB */
},
DDR3_V4L2: {
comment: "DDR3 Memory reserved for use by V4L2",
name: "DDR3_V4L2",
base: 0xBFB00000,
len: 0x00200000 /* 2 MB */
},
DDR3_SR0: {
comment: "DDR3 Memory reserved for use by SharedRegion 0",
name: "DDR3_SR0",
base: 0x9F700000,
len: 0x00200000 /* 2 MB */
},
DDR3_M3: {
comment: "DDR3 Memory reserved for use by the M3 core",
name: "DDR3_M3",
base: 0x9D500000,
len: 0x00F00000 /* 16 MB */
},
DDRALGHEAP: {
comment: "DDR3 Memory reserved for use by algorithms on the M3",
name: "DDRALGHEAP",
base: 0x9BD00000,
len: 0x01800000 /* 24 MB */
},
};

var TI816X_VPSSM3_ExtMemMap = {
DDR3_HOST: {
comment: "DDR3 Memory reserved for use by the A8",
name: "DDR3_HOST",
base: 0x80000000,
len: 0x16C00000 /* 364 MB */
},
DDR3_DSP: {
comment: "DDR3 Memory reserved for use by the C674",
name: "DDR3_DSP",
base: 0x99500000,
len: 0x00C00000 /* 12 MB */
},
DDR3_SR1: {
comment: "DDR3 Memory reserved for use by SharedRegion 1",
name: "DDR3_SR1",
base: 0x99400000,
len: 0x00100000 /* 1 MB */
},
DDR3_HDVPSS: {
comment: "DDR3 Memory reserved for use by HDVPSS",
name: "DDR3_HDVPSS",
base: 0xBF900000,
len: 0x00200000 /* 2 MB */
},
DDR3_V4L2: {
comment: "DDR3 Memory reserved for use by V4L2",
name: "DDR3_V4L2",
base: 0xBFB00000,
len: 0x00200000 /* 2 MB */
},
DDR3_SR0: {
comment: "DDR3 Memory reserved for use by SharedRegion 0",
name: "DDR3_SR0",
base: 0x9F700000,
len: 0x00200000 /* 2 MB */
},
DDR3_M3: {
comment: "DDR3 Memory reserved for use by the M3 core",
name: "DDR3_M3",
base: 0x9E600000,
len: 0x00F00000 /* 16 MB */
},
DDRALGHEAP: {
comment: "DDR3 Memory reserved for use by algorithms on the M3",
name: "DDRALGHEAP",
base: 0x9A200000,
len: 0x01B00000 /* 27 MB */
},
};

but when the firmware is loaded,the codec engine example will fail:

root@dm816x-evm:/usr/share/ti/ti-codec-engine-examples/audio1_copy# ./app_remote
.xv5T
[t=0x000041a3] [tid=0x40088000] xdc.runtime.Main: [+2] main> ti.sdo.ce.examples.apps.audio1_copy
[t=0x000048f3] [tid=0x40088000] xdc.runtime.Main: [+1] App-> Application started, procId DSP engineName remote_copy_DSP input-file ./in.dat output-file ./out.dat.
./app_remote.xv5T: error: can't open engine remote_copy_DSP
[t=0x03a10a0a] [tid=0x40088000] xdc.runtime.Main: [+1] app done.

Why?

0 _Ralph_ over 11 years ago in reply to feng xiao ming

Guru 10685 points

I might be wrong here but I think your ARM code should be trying to open a Codec Engine of name "remote_copy_dsp" and not "remote_copy_DSP".

Ralph

0 Margarita Gashova over 11 years ago in reply to feng xiao ming

TI__Guru* 80190 points

Hello,

You could try:

1.CE_DEBUG=3 ./app_remote -p DSP -s xe674

2.Rebuilding codec engine and codec engine examples

Let us know the results. If still there is a problem share the debug log.

Best Regards,

Margarita

0 feng xiao ming over 11 years ago in reply to Margarita Gashova

Expert 1445 points

Margarita and Ralph:

Thank you!,The problem has been solved.My DDR3_SR1 is not right.

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About codec engine of DM8168