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Watchdog in u-boot DM8168

Holger Eberhard102906
Genius 4570 points

Hi,

We use DM8168 in custom design based on UD-WORKS sample. We try to enable OMAP Watchdog in u-boot for DM8168.

After I enabled watchdog for testing --> I get a reset every second.

    __raw_writel(0xAAAA, WDT_WSPR);

    while(__raw_readl(WDT_WWPS) & 0x10);

    __raw_writel(0x5555, WDT_WSPR);

    while(__raw_readl(WDT_WWPS) & 0x10);

    /* Unfreeze WDT */

    __raw_writel(0x2, WDT_UNFREEZE);

    /* Sequence to enable the watchdog */

    __raw_writel(0xBBBB, WDT_WSPR);

    while(__raw_readl(WDT_WWPS) & 0x10);

    __raw_writel(0x4444, WDT_WSPR);

    while(__raw_readl(WDT_WWPS) & 0x10);

We did read in "e2e.ti.com/.../327054"

that the Watchdog timer is configured, enabled and then disabled by the DM814x ROM code (configured for 10s).

Does DM8168 ROM code does the same (10s timeout) ?

 

  • 0
    TI__Guru**** 170625 points
    Hi Holger,

    There are two silicon errata advisories regarding the DM816x WDT which are fixed (not present) for DM814x WDT.

    Advisory 1.1.37 — Watchdog Timer (WDT): Default Timeout Period of 2 ms is Too Short - for silicon revisions 1.0 and 1.1, this is applied on the DM816x TI EVM

    processors.wiki.ti.com/.../TI81XX_PSP_WDT_Driver_User_Guide

    Advisory 2.1.65 — Watchdog Timer (WDT): Watchdog Timer Generates Reset When Enabled For First Time After Power-On Reset - for silicon revisions 2.0 and 2.1

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Genius 4570 points

    Hi Pavel, thanks for reply,

    we use silicon rev. 2.0 and 2.1, but I can also test UD-Works demo hardware with rev 1.0

    I have 2 questions:

    1. If I start DM8168 in NAND boot mode an we have no u-boot in NAND I expect that Watchdog occurs after 3 minutes (SPRUGX8: "set to three minutes" ).

    Is this right?

    2. I did not found a register  WDT_UNFREEZE (CTRL_BASE + 0x100) in reference manual.

    What does the following unfreeze ?    

    /* Unfreeze WDT */     __raw_writel(0x2, WDT_UNFREEZE);

    BR Holger

  • 0 in reply to Holger Eberhard102906
    TI__Guru**** 170625 points

    Holger Eberhard102906 said:

    1. If I start DM8168 in NAND boot mode an we have no u-boot in NAND I expect that Watchdog occurs after 3 minutes (SPRUGX8: "set to three minutes" ).

    Is this right?

    Yes, the DM816x was design to act like this, if there are no other (than NAND) valid booting devices in the list, the WDT should break the dead loop after 3 minutes. But there was a silicon malfunction found and documented in the silicon errata. According to the errata 2.1.65 (for 2.x), the WDT is not enabled by ROM code (at least for GP device) (GP = General Purpose).

    Holger Eberhard102906 said:

    2. I did not found a register  WDT_UNFREEZE (CTRL_BASE + 0x100) in reference manual.

    What does the following unfreeze ?  

    CONTROL_SEC_CTRL register (from errata) is named WDT_UNFREEZE in u-boot.

    The CONTROL_SEC_CTRL register is System Security Control Register, it belongs to the device Control Module (address 0x48140000) at offset 0x0100.

    The bottom bits in the CONTROL_SEC_CTRL register are used to control the watchdog (WPOPDISABLE is obviously a misspelling in the errata).
    1
    WDRegEnable
    Secure watchdog registers update access control:
       0 Þ     Access is never allowed
       1 Þ     Access is allowed only in Secure Mode (any mode on GP device)
    0
    WDOpDisable
    Secure watchdog operation enable control:
      0 Þ     Watchdog timer is running
       1 Þ     Watchdog timer is frozen
    These bits are One-Change-Only.  For GP devices, they come up 0b11, i.e. write access allowed in supervisor mode, and watchdog timer frozen.  For HS devices, the reset value is 0b10, i.e. access allowed in secure mode only, and watchdog timer running.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Genius 4570 points

    Pavel, thanks for Your detailed explanation.

    But it is not realy clear for me:

    1. After writing 0x02 to WDT_UNFREEZE the watchdog is "Watchdog timer is running" but also disabled by writing 0xAAAA / 0x5555 to WDT_WSPR.

    A reset occurs after WDT_UNFREEZE is written or when ?

    2. If we write 0xBBBB / 0x4444 to WDT_WSPR --> the watchdog is enabled with 2ms timeout, this means uboot starts again (I can see this), OK ?  

  • 0 in reply to Holger Eberhard102906
    TI__Guru**** 170625 points

    Holger,

    Holger Eberhard102906 said:

    1. After writing 0x02 to WDT_UNFREEZE the watchdog is "Watchdog timer is running" but also disabled by writing 0xAAAA / 0x5555 to WDT_WSPR.

    A reset occurs after WDT_UNFREEZE is written or when ?

    Yes, according to the errata 2.1.65, reset should occur 2ms after writing bit [0]WDOpDisable with 0x0. And WDT reset should not be disabled with HW, like in the DM816x TI EVM, where this reset can be disabled with SW2.

    See also:

    Holger Eberhard102906 said:
    2. If we write 0xBBBB / 0x4444 to WDT_WSPR --> the watchdog is enabled with 2ms timeout, this means uboot starts again (I can see this), OK ?  

    I do not understand your question here. What do you mean u-boot to start again? You mean that WDT trigger reset after 2ms and thus u-boot start again? Or you mean something else??

  • 0 in reply to Pavel Botev
    Genius 4570 points
    Pavel, thanks for Your patience.
    I have made some tests meanwhile.
    Watchdog works as expected.
    Also I have moved omap_wdt.c functions as a template to uboot. Currently I am testing watchdog timer.
    Please Keep this thread for a while until I have success.
    BR Holger
  • 0 in reply to Holger Eberhard102906
    TI__Guru**** 170625 points
    Holger,

    I have only DM816x PG1.1 board, so I can not test the things described in errata 2.1.65. Please test on PG2.x board and share your findings.

    BR
    Pavel
  • 0 in reply to Pavel Botev
    Genius 4570 points

    Watchdog works fine now and makes uboot save for CPU Rev.2.1.
    I moved functions from /linux/drivers/watchdog/omap_wdt.c to uboot and adapt the functions for using in uboot.
    We start Watchdog erarly in uboot arch/arm/lib/start_armboot(), timeout is set to 60 seconds.
    Also added define CONFIG_HW_WATCHDOG and hw_watchdog_reset() function for trigger watchdog.
    Thank You Pavel for the support!
    BR Holger