• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 1314 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320DM8168: Quesiton about the high period of WD_OUT when wdt reset is triggered

Chris Meng
Mastermind 37646 points
Part Number: TMS320DM8168

Hi,

My customer found when wdt reset is triggered, the high period of WD_OUT pin is less than 1us.

From DM816x TRM, the functional clock source of wdt is 32khz. So the period should be ms level even with the prescalar to 1 (WDT_WCLR[4:2] PTV bit=0).

My customer also tried to change the value of PTV bit, but it seems it doesn't change the high period of WD_OUT. Customer does disable WDT before setting PVT and enable prescalar and then enable WDT to trigger WDT reset.

Would you pls kindly advise why the high period of WD_OUT is so short (less than 1us)? How to increase the high period on DM816x?

I checked the other post it seems the method for DM814x doesn't work on DM816x due to different output pin.

Thanks,

  • 0
    TI__Guru**** 170625 points
    Hi Chris,

    See if the below e2e thread will be in help:

    e2e.ti.com/.../1758192

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Mastermind 37646 points
    Pavel,

    It seems the link in my post is broke and I pointed to same link. I have checked this thread, but it can't answer my question.

    Would you pls help to check again?
  • 0 in reply to Chris Meng
    TI__Guru**** 170625 points
    Chris,

    I made a search in DM816x TRM, but I can not find a way to increase the WD_OUT pulse duration.

    Seems like this 1us duration is based on SYS_CLK/DEV_MXI/DEV_CLKIN (27MHz) and is enough for POR. You can also try to change WDT_FCLK/sysclk18/32Khz and/or WDT_ICLK/sysclk6/125MHz frequency and see if WD_OUT pulse duration will be impacted.

    Why do you need WD_OUT pulse duration adjustment? For resetting peripherals when WDT reset occur you can use RSTOUTn pin, which is asserted by WDT and its pulse duration is controlled by PRM_RSTTIME register.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Mastermind 37646 points
    Pavel,

    1. Customer has checked the sysclk18 and it can from 32Khz or Audio PLL clock 1. But there is no register which can configure Audio PLL clock 1.
    2. Customer has tried to change sysclk6, but no effect.

    Customer has made own board which uses WD_OUT to trigger the external circuit to reset the whole system, but due to removing the jitter for bottom, they add a capacity which affects WD_OUT signal due to short period pulse. So they want to increase the high period of the WD_OUT pulse.

    Would you pls help to check again if there is any way to increase the WD_OUT pulse?
  • 0 in reply to Chris Meng
    TI__Guru**** 170625 points

    Chris Meng said:
    1. Customer has checked the sysclk18 and it can from 32Khz or Audio PLL clock 1. But there is no register which can configure Audio PLL clock 1.

    See AUDIOPLL_x registers. Refer to DM816x TRM sections:

    1.10.3.1.4 Audio PLL
    1.10.3.1.4.1 Steps for Changing AUDIOPLL Frequency
    1.16.1.2 PLL Control Registers


    Chris Meng said:
    Customer has made own board which uses WD_OUT to trigger the external circuit to reset the whole system, but due to removing the jitter for bottom, they add a capacity which affects WD_OUT signal due to short period pulse.

    You can check how this is done in DM816x TI EVM. See also the below wiki:

    Chris Meng said:
    Would you pls help to check again if there is any way to increase the WD_OUT pulse?

    I checked another more time, but still can not find a SW way to increase WD_OUT pulse. You can add external HW to the WD_OUT pin which can increase the pulse.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    TI__Mastermind 37646 points

    Pavel,

    There is no register for Audio PLL clock 1. No AudioPLL_FREQ1/AUDIOPLL_DIV1.

  • 0 in reply to Chris Meng
    TI__Guru**** 170625 points
    Chris,

    Correct. Seems that Audio PLL clock 1 (sysclk18) is fixed at 32KHz and can not be changed.

    Regards,
    Pavel