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OMAPL138 PLL initialization procedure (difference of LogicPD GEL and Reference Guide)

Toshio Ushikubo
Mastermind 9620 points
Other Parts Discussed in Thread: OMAPL138, OMAP-L138

My customer has PLL initialization problem.
Please answer following questions.

Customer built 1,000 boards, and performed PLL initialization according to the OMAPL138 System Reference Guide(sprugm7e)
page 88 "8.2.2.2 Initializing PLL Mode from PLL Power Down". Their board use external clock for PLL, so they set CLKMODE bit=1 at first according to the Reference Guide. With this procedure 7/1,000 board can't be initialized PLL correctly.
So thy changed the procedure same with following LogicPD GEL file and all boards worked correctly.)
(System Reference Guide set CLKMODE bit at first but GEL file set it after wait 4 cycles, so they changed the CLKMODE initialization order same with GEL.)

******************************************************************************************************************************************************
device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

    unsigned int i=0;

    /* Clear PLL lock bit */
    CFGCHIP0 &= ~(0x00000010);

    /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
    PLL0_PLLCTL &= ~(0x00000020);

    /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
    PLL0_PLLCTL &= ~(0x00000200);

    /* Set PLLEN=0 to put in bypass mode*/
    PLL0_PLLCTL &= ~(0x00000001);

    /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
    for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

    /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
    PLL0_PLLCTL &= 0xFFFFFEFF;
    PLL0_PLLCTL |= (CLKMODE << 8);

    /*Clear PLLRST bit to reset the PLL */
    PLL0_PLLCTL &= ~(0x00000008);

    /* Disable the PLL output*/
    PLL0_PLLCTL |= (0x00000010);

    /* PLL initialization sequence
    Power up the PLL by setting PWRDN bit set to 0 */
    PLL0_PLLCTL &= ~(0x00000002);

    /* Enable the PLL output*/
    PLL0_PLLCTL &= ~(0x00000010);

    /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
    for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

    /*Program the required multiplier value in PLLM*/
    PLL0_PLLM    = PLLM;

    /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
    PLL0_POSTDIV = 0x8000 | POSTDIV;

    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL0_PLLSTAT & 0x1==1){}

    /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL0_PLLDIV1 = 0x8000 | PLLDIV1;             // Fixed Ratio /1
    PLL0_PLLDIV2 = 0x8000 | PLLDIV2;             // Fixed Ratio /2
    PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1); // Fixed Ratio /4
    PLL0_PLLDIV6 = 0x8000 | PLLDIV1;             // Fixed Ratio /1
    PLL0_PLLDIV3 = 0x8000 | PLLDIV3;             // Variable Ratio (EMIF)
    PLL0_PLLDIV7 = 0x8000 | PLLDIV7;             // Variable Ratio (RMII)


    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL0_PLLCMD |= 0x1;

    /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL0_PLLSTAT & 0x1==1) { }

    /*Wait for PLL to reset properly.*/
    for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}

    /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
    PLL0_PLLCTL |= 0x8;

    /*Wait for PLL to lock.*/
    for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}

    /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
    PLL0_PLLCTL |=  0x1;
}

******************************************************************************************************************************************************

Q1:
Please advice which is correct about initialization order of CLKMODE bit.

Q2:
According to GEL file, there are 4 cycles wait before CLKMODE bit initialization.
Is any wait cycle before CLKMODE bit initialization required ?

Regards.

  • 0
    Mastermind 9620 points

    Additional question.

    Q3:

    Please confirm if following understanding is correct.

    PLL is initialized while customer's boot program, so PLL is enabled when application program performs PLL initialization.

    PLL should be bypass mode when CLKMODE bit is changed, so customer use GEL file initialization procedure in application program.

    (Set PLL bypass mode and change CLKMODE bit next)

     

    Regards. 

     

  • 0 in reply to Toshio Ushikubo
    TI__Genius 17355 points

    The GEL file initialization procedure matches with the procedure that we use in the ROM boot loader.  Given that it works, I would recommend using it.  We will need to investigate further whether the four cycle delay is an absolute requirement that should be documented.  As an experiment, the customer could consider using the exact procedure from the GEL file except only removing that delay (so we can eliminate any other variations).  If the failures return, then that will be a compelling argument that the delay is required.

    Regards, Daniel

  • 0 in reply to Daniel Allred
    TI__Genius 17355 points

    The current OMAP-L138 TRM does show a 4 cycle wait is required, but it also shows that the CLKMODE bit is set before putting the PLL in bypass.  So I think some more investigation is in order.

    Regards, Daniel

  • 0 in reply to Daniel Allred
    Mastermind 9620 points

    Thank you for your answer.

    I have additional question about LogicPD GEL file.

    Q4:
    GEL file has following procedure in device_PLL0( ) function.

    1)  /* Disable the PLL output*/
        PLL0_PLLCTL |= (0x00000010);

    2)  /* PLL initialization sequence
        Power up the PLL by setting PWRDN bit set to 0 */
        PLL0_PLLCTL &= ~(0x00000002);

    3)  /* Enable the PLL output*/
        PLL0_PLLCTL &= ~(0x00000010);

    But following PLL initialization procedure explained in the Reference Guide（SPRUGM7E）
    page 88 doesn't have 1) and 3).

    　・8.2.2.2 Initializing PLL Mode from PLL Power Down
    　・8.2.2.3 Changing PLL Multiplier(If the PLL is not powered down)

    　
    * Please explain why GEL file has procedure 1) and 2).

    * Procedure 3) write "0" to bit4(reserved) but Reference Guide（SPRUGM7E）page 93 said
      that "Reserved.Write the default value when modifying this register.".
      Default value of bit4 is "1".
      Please let me confirm that above procedure 3) is wrong operation.
     
      Regards.

  • 0 in reply to Toshio Ushikubo
    Mastermind 9620 points

    Above my question was incorrect.

    Following is correction of my question.

    <Incorrect>

    * Please explain why GEL file has procedure 1) and 2).

     

    <Correct>

    * Please explain why GEL file has procedure 1) and 3)

     

    Regards.

  • 0 in reply to Toshio Ushikubo
    TI__Genius 17355 points

    Looking at the PLL controller spec, steps 1 and 3 are not mentioned as a requirement for enabling the PLL or changing the multiplier settings.  The bit 4 referenced in these steps is a disable bit for the the PLL.  Based on my understanding of the spec and also based on the current public documnetation, I believe these two steps are not actually required. It's conceivable that they don't actually do anything, depending on the connection between the controller and the PLL itself.

    As for why they exist in the GEL file, I can't answer that.  But again, all the documentation points to the fact that these statements can be removed.

    Regards, Daniel