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EPWM issue

 Customer query
---
I have tried to persuade the eHRPWM1 to produce 1/6 of the ASYNC3 clock on the B output by
letting it count down and toggle on zero.
My plan is to stop- and start it by changing the AQCTLB register between 1 and 3 on the fly.
But it doesn't work. Apparently it doesn't even start.
What's wrong? What did I miss? Do you have a clue?
 
The code is:
 
typedef struct epwm_s {
// Time-Base Submodule Registers
    volatile u16    tbctl;          // 00h  Time-Base Control Register
    volatile u16    tbsts;          // 02h  Time-Base Status Register
    volatile u16    tbphshr;        // 04h  Extension for HRPWM Phase Register (2)
    volatile u16    tbphs;          // 06h  Time-Base Phase Register
    volatile u16    tbcnt;          // 08h  Time-Base Counter Register
    volatile u16    tbprd;          // 0Ah  Time-Base Period Register (Shadow)
             u16    res1;           // 0Ch
// Counter-Compare Submodule Registers
    volatile u16    cmpctl;         // 0Eh  Counter-Compare Control Register
    volatile u16    cmpahr;         // 10h  Extension for HRPWM Counter-Compare A Register (2)
    volatile u16    cmpa;           // 12h  Counter-Compare A Register (Shadow)
    volatile u16    cmpb;           // 14h  Counter-Compare B Register (Shadow)
// Action-Qualifier Submodule Registers
    volatile u16    aqctla;         // 16h  Action-Qualifier Control Register for Output A (EPWMxA)
    volatile u16    aqctlb;         // 18h  Action-Qualifier Control Register for Output B (EPWMxB)
    volatile u16    aqsfrc;         // 1Ah  Action-Qualifier Software Force Register
    volatile u16    aqcsfrc;        // 1Ch  Action-Qualifier Continuous S/W Force Register Set (Shadow)
// Dead-Band Generator Submodule Registers
    volatile u16    dbctl;          // 1Eh  Dead-Band Generator Control Register
    volatile u16    dbred;          // 20h  Dead-Band Generator Rising Edge Delay Count Register
    volatile u16    dbfed;          // 22h  Dead-Band Generator Falling Edge Delay Count Register
// Trip-Zone Submodule Registers
    volatile u16    tzsel;          // 24h  Trip-Zone Select Register
             u16    res2;           // 26h
    volatile u16    tzctl;          // 28h  Trip-Zone Control Register (3)
    volatile u16    tzeint;         // 2Ah  Trip-Zone Enable Interrupt Register (3)
    volatile u16    tzflg;          // 2Ch  Trip-Zone Flag Register (3)
    volatile u16    tzclr;          // 2Eh  Trip-Zone Clear Register (3)
    volatile u16    tzfrc;          // 30h  Trip-Zone Force Register (3)
// Event-Trigger Submodule Registers
    volatile u16    etsel;          // 32h  Event-Trigger Selection Register
    volatile u16    etps;           // 34h  Event-Trigger Pre-Scale Register
    volatile u16    etflg;          // 36h  Event-Trigger Flag Register
    volatile u16    etclr;          // 38h  Event-Trigger Clear Register
    volatile u16    etfrc;          // 3Ah  Event-Trigger Force Register
// PWM-Chopper Submodule Registers
    volatile u16    pcctl;          // 3Ch  PWM-Chopper Control Register
} epwm_t;
 
extern far epwm_t   _epwm0;
extern far epwm_t   _epwm1;
void epwm_setup(epwm_t *e, u16 div)
{
    int i0;
    _cfgchip[1]&= ~(1<<12);// TBCLKSYNC
    for (i0 = 0; i0 < 31; i0++) ((u16 *)e)[i0] = 0;
    e->tbctl    = 0;       // stop
    e->tbsts    = 0;
    e->tbphs    = 0;
    e->tbphshr  = 0;
    e->tbcnt    = div;
    e->tbprd    = div;
   
    e->cmpctl   = 0;        // Load on tbcnt = 0
    e->cmpahr   = 0;
    e->cmpa     = 0;
    e->cmpb     = 0;
   
    e->aqctla   = 0;
    e->aqctlb   = 3;        // toggle b on (cnt == 0)
    e->aqsfrc   = 0;
    e->aqcsfrc  = 0;
   
    e->dbctl    = 0;
    e->dbred    = 0;
    e->dbfed    = 0;
   
    e->pcctl    = 0;
   
    e->tzsel    = 0;
    e->tzctl    = 0;
    e->tzeint   = 0;
    e->tzclr    = 7;        // clear all interrupts
    e->tzfrc    = 0;
   
    e->etsel    = 0;
    e->etps     = 0;
    e->etclr    = 1;        // clear flag
 
    e->tbctl    = 0xC071;   // Free run, no EPWMxSYNC0, count down, force sync
    _cfgchip[1]|=   (1<<12);// TBCLKSYNC
 
    p(" EPWM started");

 

  • Issue Resolution

    ---

    The issue turned out to be that customer was writing to CFGCHIP1 register ( _cfgchip[1]|=   (1<<12);// TBCLKSYNC), in user mode. This register can only be configured in Supervisor mode. 

    Additionally, such privliege errors for accesses to SYSCFG module can be caught by configuring the SYSCFG PROTERR interrupt (details in  System Guide, SYSCFG chapter. Interrupt # 74 on DSP and #27 on AINTC

    Regards

    Mukul