McASP receive clock failure on OMAP-L137 DSP

Eugene C

Other Parts Discussed in Thread: OMAP-L137

Hi,

On my OMAP-L137 DSP non-BIOS, I configured a McASP port as receiver, with burst mode, as only 1 channel of data for every frame sync signal.

I follow the initialization steps on Section 2.4.1.2 (page 35) of TMS320C674x/OMAP-L1x Processor Multichannel Audio Serial Port (McASP) User's Guide.

I am using the internal clock source (AUXCLK or SYSCLK_2) to generate the AHCLKR and ACLKR. However, there is always the receiver clock failure.

My questions are:

(1). For AHCLKRCTL register, the internal clock source to generate the AHCLKR, which clock source is used, AUXCLK or SYSCLK_2?

On the PLL reference guide, it mentions that McASP system clock is from DSP SYSCLK_2, while the McASP serial clock is from AUXCLK. It is very confusing.

(2). If we want to use the McASP burst receive mode, do we need to configure the RCLKCHK register?

On Section 2.4.2.1 (page 39) of the McASP user guide, it mentions RCLKCHK/XCLKCHK is not applicable. Leave at default. However, the receiver clock failure problem is related to RCLKCHK register.

(3). How to decide the proper values of RMAX, RMIN, and RPS of the RCLKCHK register, to eliminate the receiver clock failure problem?

(4). How to recover from the clock failure?On the steps presented in the user guide, is the measurement taken automatically by the DSP? How to achieve to wait until first measurement is taken (> 32 AHCLKR clock periods?.

For the receive clock failure check steps:
a. Configure receive clock failure detect logic (RMIN, RMAX, RPS) in the receive clock check control
register (RCLKCHK).
b. Clear receive clock failure flag (RCKFAIL) in the receive status register (RSTAT).
c. Wait until first measurement is taken (> 32 AHCLKR clock periods).
d. Verify no clock failure is detected.
e. Repeat steps b–d until clock is running and is no longer issuing clock failure errors.
f. After the receive clock is measured and falls within the acceptable range, the following may be
enabled:
i. receive clock failure interrupt enable bit (RCKFAIL) in the receiver interrupt control register
(RINTCTL)
ii. mute option (RCKFAIL) in the mute control register (AMUTE)

Thank you.

over 13 years ago

0 dabuan over 13 years ago

TI__Genius 14545 points

Eugene

Eugene C said:

(1). For AHCLKRCTL register, the internal clock source to generate the AHCLKR, which clock source is used, AUXCLK or SYSCLK_2?

On the PLL reference guide, it mentions that McASP system clock is from DSP SYSCLK_2, while the McASP serial clock is from AUXCLK. It is very confusing.

There are two things to consider here

1. The McASP module needs a clock source to clock its internal logic (SYSCLK_2). This is usually much much faster than the clock associated with the Audio data bits.

2. The Clocking for the the Audio Data Bits can be generated by a Divide down of either AUXCLK or an external clock source.

So you need both to operate the McASP.

Eugene C said:
(2). If we want to use the McASP burst receive mode, do we need to configure the RCLKCHK register?

Not for burst mode. Make sure you have all other registers programmed for burst mode operation. Example would be AFSXCTL, AFSRCTL, etc..

Eugene C said:
(3). How to decide the proper values of RMAX, RMIN, and RPS of the RCLKCHK register, to eliminate the receiver clock failure problem?

These must be calculated based upon how many SYSCLK2 clocks are generated for a given 32 AHCLKR cycles. Should be a don't care for Burst mode.

0 dabuan over 13 years ago

TI__Genius 14545 points

Eugene

Eugene C said:

(1). For AHCLKRCTL register, the internal clock source to generate the AHCLKR, which clock source is used, AUXCLK or SYSCLK_2?

On the PLL reference guide, it mentions that McASP system clock is from DSP SYSCLK_2, while the McASP serial clock is from AUXCLK. It is very confusing.

There are two things to consider here

1. The McASP module needs a clock source to clock its internal logic (SYSCLK_2). This is usually much much faster than the clock associated with the Audio data bits.

2. The Clocking for the the Audio Data Bits can be generated by a Divide down of either AUXCLK or an external clock source.

So you need both to operate the McASP.

Eugene C said:
(2). If we want to use the McASP burst receive mode, do we need to configure the RCLKCHK register?

Not for burst mode. Make sure you have all other registers programmed for burst mode operation. Example would be AFSXCTL, AFSRCTL, etc..

Eugene C said:
(3). How to decide the proper values of RMAX, RMIN, and RPS of the RCLKCHK register, to eliminate the receiver clock failure problem?

These must be calculated based upon how many SYSCLK2 clocks are generated for a given 32 AHCLKR cycles. Should be a don't care for Burst mode.

Eugene C said:
(4). How to recover from the clock failure?On the steps presented in the user guide, is the measurement taken automatically by the DSP? How to achieve to wait until first measurement is taken (> 32 AHCLKR clock periods?.

Power Cycle the McASP Module using the Power & Sleep Controller, and then reinitialize.

0 Eugene C over 13 years ago in reply to dabuan

Prodigy 190 points

hi, Drew,

Thank you for the reply.

May I know how to power cycle the McASP module stand-alone using the Power & Sleep controller? I follow the steps presented in the GEL file, to set the PSC1_McASP1_MDCTL register to Disable state at first, then set it to Enable state again to reset the McASP1 module, is it correct? However, after doing this, the McASP module still reports receive clock failure problem.

My steps to reset the McASP module is below. Could you check for me where is the problem? Thank you.

////////////////////////////

#define PSC1_MDCTL                 (PSC1_BASE+0xA00)
#define PSC1_MDSTAT             (PSC1_BASE+0x800)
#define PSC1_PTCMD             *(unsigned int*) (PSC1_BASE + 0x120)
#define PSC1_PTSTAT             *(unsigned int*) (PSC1_BASE + 0x128)

#define PSC1_McASP1_MDCTL         *(unsigned int*) (PSC1_BASE + 0xA00 + 0x32)        // McASP1 is MDSTAT_8

#define PSC1_McASP1_MDSTAT *(unsigned int*) (PSC1_BASE + 0x800 + 0x32) // McASP1 is MDSTAT_8

void Power_off_McASP1( )
{
    PSC1_McASP1_MDCTL = (PSC1_McASP1_MDCTL & 0xFFFFFFF8) | (2 << 0);

    PSC1_PTCMD = 0x1<<0;

    while( (PSC1_PTSTAT & (0x1<<0) ) !=0) ;    /*Wait for power state transition to finish*/

    while( (PSC1_McASP1_MDSTAT & 0x1F) !=0x2);

}

void Power_on_McASP1( )
{
    PSC1_McASP1_MDCTL = (PSC1_McASP1_MDCTL & 0xFFFFFFF8) | (3 << 0);

    PSC1_PTCMD = 0x1<<0;

    while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/

    while( (PSC1_McASP1_MDSTAT & 0x1F) !=0x3);

}

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McASP receive clock failure on OMAP-L137 DSP