Hi. I'm working on an OMAP-L138 board, and I'm trying to get the DSP core to talk to an external peripheral with memory-mapped registers. I've spent the last day banging my head against the wall and getting nowhere. Bottom line: I never see EMIFA_CS2# assert, so my peripheral never responds. Here's what I've checked....
I made a .tci file for the memory map, and included it in my project .tcf file:
/* ============================================================================
* FPGA Registers EMIF peripheral
* ============================================================================
*/
var FPGA_REGS = prog.module("MEM").create("FPGA_REGS");
FPGA_REGS.base = 0x60000000;
FPGA_REGS.len = 0x2000000;
FPGA_REGS.space = "data";
FPGA_REGS.createHeap = false;
FPGA_REGS.comment = "FPGA_REGS";
prog.module("GBL").C64PLUSMAR96to127 = 0x00000000 ;
...marked all of EMIF space not cacheable.
Declared the registers in C like this...
static volatile far __attribute__((__section__(".fpga_regs")))
struct fpga_registers {
/* blah, blah, blah.... */
} fpga_regs;
...and mapped them to the right address with this snippet of linker command file:
.fpga_regs: {
*(.fpga_regs)
} > FPGA_REGS
in a SECTIONS declaration.
Wrote up a little test function to read a register, increment the value, and write it back. If I look at the post-link disassembly of that function, it goes like this:
c23962a0 0203b80e LDHU.D2T2 *+B14[952],B4
c23962a4 01800328 MVK.S1 0x0006,A3
c23962a8 01b00069 MVKH.S1 0x60000000,A3
c23962ac 000c0362 || B.S2 B3
c23962b0 020c0204 LDHU.D1T1 *+A3[0],A4
c23962b4 0c6e NOP 1
c23962b6 2651 ADD.L2 B4,1,B5
c23962b8 0283b85e STH.D2T2 B5,*+B14[952]
c23962bc e4000000 .fphead n, l, W, BU, nobr, nosat, 0100000b
c23962c0 020c0256 STH.D1T2 B4,*+A3[0]
That sure looks like a read from, and subsequent write to address 0x60000006, the fourth 16-bit register in the map.
EMIFA is enabled in the PINMUX, and CE2 is configured for the most conservative possible timings...
/* configure the pinmux for the EMIFA -- pins (BA[1:0], CLK, CS2, OE#,
* WE#, RNW, WAIT[1:0], DATA[15:0], ADDR[13:0] */
tmp = (sysCfgRegs->PINMUX5 & 0x00FFFFFF) | 0x11000000;
sysCfgRegs->PINMUX5 = tmp;
tmp = (sysCfgRegs->PINMUX6 & 0xF0FFFFF0) | 0x01000001;
sysCfgRegs->PINMUX6 = tmp;
tmp = (sysCfgRegs->PINMUX7 & 0x0000FFF0) | 0x11110001;
sysCfgRegs->PINMUX7 = tmp;
tmp = (sysCfgRegs->PINMUX8 & 0x00000000) | 0x11111111;
sysCfgRegs->PINMUX8 = tmp;
tmp = (sysCfgRegs->PINMUX9 & 0x00000000) | 0x11111111;
sysCfgRegs->PINMUX9 = tmp;
tmp = (sysCfgRegs->PINMUX10 & 0xFFFFFFFF) | 0x00000000;
sysCfgRegs->PINMUX10 = tmp;
tmp = (sysCfgRegs->PINMUX11 & 0x000000FF) | 0x11111100;
sysCfgRegs->PINMUX11 = tmp;
tmp = (sysCfgRegs->PINMUX12 & 0x00000000) | 0x11111111;
sysCfgRegs->PINMUX12 = tmp;
emifaRegs->CE2CFG =
(CSL_EMIFA_CE2CFG_SS_SELSTRB_DISABLE << CSL_EMIFA_CE2CFG_SS_SHIFT)
| (CSL_EMIFA_CE2CFG_EW_EXT_WAIT_DISABLE << CSL_EMIFA_CE2CFG_EW_SHIFT)
| (0x0F << CSL_EMIFA_CE2CFG_W_SETUP_SHIFT)
| (0x3F << CSL_EMIFA_CE2CFG_W_STROBE_SHIFT)
| (0x07 << CSL_EMIFA_CE2CFG_W_HOLD_SHIFT)
| (0x0F << CSL_EMIFA_CE2CFG_R_SETUP_SHIFT)
| (0x3F << CSL_EMIFA_CE2CFG_R_STROBE_SHIFT)
| (0x07 << CSL_EMIFA_CE2CFG_R_HOLD_SHIFT)
| (0x03 << CSL_EMIFA_CE2CFG_TA_SHIFT)
| (CSL_EMIFA_CE2CFG_ASIZE_16BIT << CSL_EMIFA_CE2CFG_ASIZE_SHIFT);
I never see CE2# go low. I see EMA_CLK toggling at the correct rate. My DSPCLK is 456MHz; if I configure the EMIF to run from the fixed DIV4.5, then I see a nice 101.3MHz clock on EMA_CLK. If I configure it to run from SYSCLK3, and make PLL0_PLLDIV3 a divide by 5, then I see a nice 91.2MHz clock on EMA_CLK. But I never see CE2# fire. And I know the test code is running -- it's returning me bogus values that it supposedly read from the register.
OK, what am I missing? What haven't I looked at that could be causing me not to get real EMIF bus accesses? Thanks much for any thoughts or pointers...
-------Carl
