Driver strength for mDDR supported [L138]

Hi Mukul,

Could you please as well confirm that:
- SDCR.DDRDRIVE0 is the LSB
- SDCR.DDRDRIVE1 is the MSB
of the DDRDRIVE[1:0] bitfield?

The reason for asking is that this is not precisely described at page 380 of TRM - SPRUH77a.
Also since the 2 bits are separated in the registers (bit 24 and 18 respectively) it makes it unclear.

The reason behind is that customer is testing an OMAP-L138 and mDDR PCB lot. It seems to pass for full and 1/4 drive strength but fails for 1/2 drive strength. If the bitfield would have been inverted then it could explain the results.

Thanks in advance and best regards,

Anthony

AnBer said:

Could you please as well confirm that:
- SDCR.DDRDRIVE0 is the LSB
- SDCR.DDRDRIVE1 is the MSB
of the DDRDRIVE[1:0] bitfield?

Anthony the above is correct.

Might need more details on your customer failure issue.

Hi Mukul, I raised this question and I was asking if it was possible that these bits are switched on-route to the mDDR device extended mode register.

We have a small percentage of our prototypes proving to be unreliable with the setting of 01, i.e. 1/2 drive strength mDDR, which approximates to 55R with Micron mDDR. This was our target PCB impedance, so should work reliably! If I set the drive strength to any other value (full, 1/4 or 3/4) then the failing boards work reliably. I'm struggling to understand this.

However, if the two DDRDRIVE bits were somehow switched, this might be easier to understand, because in this situation we'd be setting the drive strength to 1/4, whereas 1/2, 3/4 and full would be working.

I'm hoping to look at this with a decent active probe and scope on a dev PCB with some exposed traces but at the moment the combination isn't available.

Thanks, Jon.

Jon

There is a typo in the documentation, which will be fixed soon, however this might still not explain what you are seeing.

The DDRDRIVE bit fields as defined in the documentation (LSB and MSB etc) are fine and not switched

DDRDRIVE[1:0]

00: Set to Full Drive Strength

01: Set to 1/2 Drive Strength

10:  Set to 1/4 drive strength

11: Set to 1/8th drive strength (typo here in the doc where it says 3/4)

I am assuming when you will be able to measure/scope it, it will be closer to the mDDR device.

Regards

Mukul

Additionally  the DDRDRIVE[1:0] is written to bits 6:5 in the mDDR’s Extended Mode register. Bit 7 in the Extended Mode register is always set to 0.

Hi Mukul

Surely these bits are passed to the mDDR and it decides it's own drive strength? The LPDDR spec states the value 11 is optional and should result in "...Octant Strength Driver". However, Micron mDDR datasheets suggest the value 11 (or rather 011) will result in 3/4 drive strength.

I'm assuming that the L138's drive strength is set soley by the external resistor on DDR_ZP and the VTP IO buffer calibration cycle.

Regards, Jon.

What is the value on DDR_SLEW register in your case.

Regards

Mukul

Value is 0x0000 0030 (confirmed via a Lauterbach JTAG debugger rather than just checking what the software intends to set). I read as pull downs enabled, CMOS receiver type, which I believe is correct for mDDR?

Thanks, Jon.

Yes that is the correct value.

I assume for VTP calibration you rely on the RBL and not doing it again your user boot code?

We're using UBL/UBoot on the prototypes for now, and we don't normally re-run the calibration in our application, but I've also tried re-running the entire setup and calibration process using a completely independent script I wrote in the Lauterbach. The outcome is the same - 01 (1/2) is unreliable on a small number of boards, 00 (full), 10 (1/4) and 11 (3/4) are reliable.

Thanks, Jon. 

Just to update this, I can confirm that the bits are the correct way round and that there is no mistake in the docs - I see increasing drive strength going from the 1/4 through to the full strength setting.

I'm currently going back through our simulations investigating worst case scenarios including PCB variations. There is one possible issue to investigate, though it looks worse on the 1/4 setting which works fine.

Thanks, Jon.