Read/write access through emifa to fpga

Hi Reshma ,

I am not sure w.r.t VHDL side , but for emif basic flow can be:-

a) The first stage  i would suggest is you have an rev.id of your FPGA , try to get this revision ID with your code .

b) Configuring the PINUMUX

    //---CONFIGURING THE PINMUX 5
    intrpointer=(unsigned int *)(PINMUX_START  + 0x4) ;
    return_value=(*intrpointer);
    return_value = (return_value & 0xFF000000 ) ;
    return_value = (return_value | 0x11000000 ) ;
    (*intrpointer) = return_value;
    return_value=0;

   Similarly you need to first programm for all the PINMUX [#define PINMUX_START             0X01C14130  ]

c) Once PINMUX and Configuration register are programmed you can do an read and write directly

      return_value = *(unsigned short *) (EMIF_CHIP4_BASE + FPGA_ADDR);

      [ #define EMIF_CHIP4_BASE     0X64000000   ]

      unsigned short as emif is 16 bit.

d) To do an read and write to EMIF will be as simple as accessing an memory address of your processor using POINTER as mentioned above

e) We have faced a lot of issue as the address pins of PROCESSOR were not mapped to FPGA correctly due to which we were seeing an

   ADDRESS shift.

   SO just make sure that you do proper mapping of ADDRESS lines as per TRM of processor

Feel free to let me know if i can help any further !!!!!!!!!!

Ashish Kumar Mishra

[Banglore / India ]

Hi Ashish

Thanks so much for your reply. It does help a lot. 

In order to set the PINMUX registers do I have to set the KICK0 or KICK1 registers? Can you please elaborate on what you meant by proper mapping of the address lines? How is a read request to the EMIF generated? I didnt understand that part. I understood how to read. On what basis do we select the CE space?

Thanks and Regards

Reshma Angelin

Hi Reshma , 

1. I haven't used KICK register , so not sure of there use . 

2. I am trying to explain the basic flow to configure EMIF & read let us say revision ID of your FPGA  :- 

   ->  You will be mapping your FPGA to some CHIP SELECT let us say "X" ....

   ->   I have used LINUX as an reference [ we have also done with DSP part of SOC using DVSDK ]

    a) Now to access the FPGA from master , you have to access this memory i.e [ CS+OFFSET ]

         This accessing can be done easily using pointer reference & de-reference mechanism  

    b) Now what ever you write at this address [ CS+OFFSET ] should be reflected to your FPGA address , for which you have to 

        configure your EMIF interface 

        Understand that if you are not properly configuring the EMIF properly , you wont get the address & data signal at the FPGA 

         even tough you r doing read & write from your master processor [ ARM or DSP core of SOC]

    c) Now the EMIF in an interface of which pins are multiplexed .You by doing PINUMUX operation , you have to make sure 

         that EMIF has all required pins properly configured [i.e assigned to EMIF]

    d) Also since you are interacting to FPGA , you need to set timing parameters of EMIF bus in correspondence  to your RTL logic 

        Do do this setting we can use CHIP[X]_CONTROL_REGISTER. 

     So till point [ d ] we have achieved is  TIMING PARAMETERS are configured , PINMUX ing is done . 

     Now the only pending part is performing read / write operation which is explained above 

e) For addressing you can refer " 20.2.5 Asynchronous Controller and Interface " from the TRM under EMIF sub section 

Hope this should reolve you doubts and help you !!!!!!!!!!!!!!

Ashish Mishra 

[Bangalore / India]

Hi Ashish

Thanks a lot. Will get back to you if I have anymore doubts.

Regards

Reshma Angelin

Hi Ashish

       Can you please tell me on what basis is the chip select chosen? I know that CS2 is used for NOR flash, CS3 is used for NAND flash and CS0 for SDRAM. For a RAM generated in the FPGA can either of CS4 or CS5 be chosen?

Thanks and regards

Reshma Angelin

Hi Reshma , 

Not sure if you have figured it or not ...so just in case if it helps ....

yes we can acess FPGA using either CS4 or CS5 ..

We are making use of both the CS ...

Ashish Mishra 

[Banglore / India]

Hi Ashish

Thanks for your reply.

But I think we can also use CS2 and CS3 to access the fpga. As it acts as nand flash or nor flash only if a particular register for it has been set, such as the NANDFCR (NAND Flash Control Register). Am I right? And thanks a lot for your previous replies. It helped me to understand a lot.

Regards

Reshma Angelin