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Link to test code for emif (omap L138b) interface to fpga

Hi

Is there a link where I can find some example code for the emif interface to fpga?

Regards

Reshma Angelin

  • Hi Reshma,

                Here is the list of Development kits available for OMAP-L138B C6 Integra DSP+ARM processor.

    http://www.ti.com/product/omap-l138#desKit

    These design kits and evaluation modules test codes can be downloaded Logic PD website based on the kit you have purchased after registering your kit with them.

    Hope this helps.

    Regards,

    Iyshwarya

    If this answers your question, please click the Verify Answer button below. If not, please reply back with more information.

  • Hi Reshma , 

    I havent used any SAMPLE code to test the EMIF interface , so cant help u on that part but:-

    a. If you have the interface cleared the by doing basic pointer's acess you can acess an location of FPGA [which can have some known value]

        We had FPGA Rev ID for the same . 

    b. You can also use BUS ANALYZER like CHIP SCOPE  to check is you are getting any BUS transaction on the interafece

    Ashish Mishra 

    [Banglore /India ]

  • Hi

    Thank you guys. Will get back to you if I have any problems.

    Regards

    Reshma Angelin

  • Hi

         What are the test cases you guys tested, for the emif - fpga interface? Other than the checking of a memory location,eg : Rev ID of fpga?

    Regards

    Reshma Angelin

  • Hi Reshma , 

    Not sure if the reply will be helpful as we have missed your post earlier. 

    1. You can have an led connected to one of FPGA memory. 

         So you should be in a position to toggle the LED from CPU via EMIF interafce 

    2. On same line you can bring one GPIO line from FPGA, toggling should give you an square 

       wave of certain frequency at that PIN. 

    3. Also you can write some 1K buffer to FPGA and read i back from FPGA . Also in FPGA you can add an 

        offset to the data which you get as an input.Like if you get 'X' add an offset of 2 to it in ur FPGA logic  

        So when you read back the data , you should get all the buffer contents added with an offset of two. 

    If these test are through , you can rest ensure that your EMIF FPGA interface is clear 

    Ashish Mishra 

    [Banglore / India]

  • Hi Reshma,

    Have you found the solution to access fpga from omapl-138? If you have, would you share with me?

    Thank you

    Joe

  • Hi Joe


    I haven't yet tested on board. Once I get it working on board I will let you know how to do it. You can check out my other links. The replies I received to my queries may help you too.

    Regards
    Reshma Angelin

  • dear Reshma:

    do you have finished comnunication , EMIFA with FPGA?Now,I'm working for this, can you help me?

    I confige EMIFA registers( using NandFlash_Register_Calc_v3),it come from http://processors.wiki.ti.com/index.php/Programming_Asynchronous_EMIF_on_OMAP-L13x_/_C674x_/_AM1x.

    But 6748 dsp cant get any information. Can you give me a example?

    Thanks!

                                                                Lucy