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OMAPL-138: Synchronize all eCAP modules with SWSYNC

Arya Ba
Intellectual 690 points
Other Parts Discussed in Thread: OMAP-L138

Hi All,

(On the c6000 core, not the ARM)

We are attempting to Synchronize the eCAP0-eCAP2 counter (TSCTR) on start up using the SWSYNC from eCAP0. All of the eCAPs are configured as follows:

  • All eCAPs in CAPMODE
  • All are in ONE SHOT mode
  • On eCAP0 (Master for syncing)
    • SYNCI_EN is 0 (DISABLE)
    • SYNCO_SEL is  0 (SYNCIN)
    On eCAP1
    • SYNCI_EN is 1 (ENABLE)
    • SYNCO_SEL is 0 (SYNCIN)
    On eCAP2
    • SYNCI_EN is 1 (ENABLE)
    • SYNCO_SEL is 2 (DISABLE)

Once finished, we set SWSYNC to 1 on the eCAP0 to sync all eCAPs. However, none of the capture port TSCTR registers reflect the value of their corresponding shadow register CTRPHS. We were wondering if there is a caveat on using the SWSYNC (instead of the PWM Pulse) to sync that we are missing.

Thank you,

Arya B.

  • 0
    Intellectual 690 points

    Hi All,

    Upon further investigation we found on a single eCAP0, if SYNCI_EN is 1 (ENABLE) setting the SWSYNC to 1 will result in the TSCTR loading the shadow register CTRPHS. However, that sync signal is not propagating to the slave eCAP modules. Therefore, in our aforementioned configuration, on a SWSYNC the master eCAP0 TSCTR will load the shadow register CTRPH but the slave eCAP1-eCAP2 continue using their old values. We would appreciate any feedback regarding this problem.

     

    Thanks,

    Arya B.

  • 0 in reply to Arya Ba
    TI__Mastermind 20790 points

    Arya,

    The ECAPSyncInOutSelect API call can be used to disable syncIn or to enable counter to be loaded from CNTPHS register upon a SYNCI signal. I hope each of the eCAP's have the ability to be programmed independent of each other. You should be able to generate a different waveform on each channel (APWM0, 1, & 2). Please refer the ecap driver code at the OMAP-L138 Starterware package.

    syncIn can take following macros.
    ECAP_SYNC_IN_DISABLE.
    ECAP_ENABLE_COUNTER - Enables counter to load from CNTPHS register upon SYNCI signal.

    // SYNCO_SEL bit
    #define EC_SYNCIN 0x0
    #define EC_CTR_PRD 0x1
    #define EC_SYNCO_DIS 0x2

    Note:
    Whenever TSCTR = Period value of eCAP1 module is the Master and issues a sync out pulse to the slaves(modules 2, 3) .
    This wiki link will help for sync the ecap. You can take this example as a reference and use it for OMAP-L138. 
    http://processors.wiki.ti.com/index.php/C6747_eCAP_to_EHRPWM_example