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Max Frequency of 64-Bit Timer Plus (tms320c6748)

d sandquist
Prodigy 160 points
Other Parts Discussed in Thread: OMAP-L138, TMS320C6748

I've reviewed several resources and just want to verify if I understand correctly what the maximum speed of the 64-Bit Timer is.  I'm controlling a tms320c6748.  Looking at the OMAP-L138 C6-Integra™ DSP+ARM® Processor Data Sheet Ch 5.30.1 (p.255) lists the Timer Input minimum cycle time as 4*P where P = OSCIN cycle time in nsec.

OSCIN is limited to 12 to 30 MHz (Ch 5.5 p 87) meaning the counter is limited to 3 to 7.5 MHz.  Am I correct?


I couldn't find timing specs for the eCAP devices, but even if they are fast enough (I'd like >66 MHz) 3 signals are too few.  I need to count frequency on 4 signals and require 5 counters each with a 2 to 4 capture registers.

Please let me know if I have the specs correct.

  • 0
    TI__Guru*** 125430 points

    d sandquist said:
    OSCIN is limited to 12 to 30 MHz (Ch 5.5 p 87) meaning the counter is limited to 3 to 7.5 MHz.  Am I correct?

    Your comment is correct in the context of using the timer with an external time base.  That external time base can only operate up to OSCIN/4.

    d sandquist said:
    I couldn't find timing specs for the eCAP devices, but even if they are fast enough (I'd like >66 MHz) 3 signals are too few.  I need to count frequency on 4 signals and require 5 counters each with a 2 to 4 capture registers.

    The eCAP itself operates off an internal clock at the ASYNC3 clock rate.  Depending on how you've configured the ASYNC3 clock source and depending on your operating point, this could vary from 50 MHz to 228 MHz.

  • 0 in reply to Brad Griffis
    Prodigy 160 points

    Hey, Brad, thanks for the answer.  I plan to use four to six external sources in the tens of kHz range, but want one or two counters/timers to run off an internal clock.  This is a frequency measuring application.

    Noting that you placed "with an external time base" in parenthesis, what are the internal sources available for the 64 bit counter/timer and what are their rates? 

    If you could point me to where this is found along with how to set it up, I'd appreciate it.  A pointer to an example (described or in code) would also be appreciated :)

    Thanks again.

  • 0 in reply to d sandquist
    TI__Guru*** 125430 points

    The best reference would be the OMAP-L138 TRM Section 7 "Device Clocking".  Table 7-2 "System Clock Domains" shows timers 0-1 are clocked by PLL0_AUXCLK, and timers 2-3 are clocked by the ASYNC3 domain.

    You can further understand PLL0_AUXCLK from Figure 8-1 "PLLC Structure" which shows AUXCLK is just a pass-through of OSCIN.


    FYI, I noticed the following in the Timers chapter of the TRM:

    • "The external clock source frequency must be no greater than the timer peripheral reference clock (see your device-specific data manual)."

    In hind sight I think that section of the DM might possibly have been incomplete.  In particular, I think Timers 2-3 should probably be relative to ASYNC3 (i.e. 1/4 * ASYNC3).  Let me see if I can get clarification on that...

  • 0 in reply to Brad Griffis
    TI__Guru* 84775 points

    Brad Griffis said:
    In hind sight I think that section of the DM might possibly have been incomplete.  In particular, I think Timers 2-3 should probably be relative to ASYNC3 (i.e. 1/4 * ASYNC3).  Let me see if I can get clarification on that...

    Brad your assessment on Timer 2-3 is correct.  It should be relative to ASYNC3. 

  • 0 in reply to Mukul Bhatnagar
    TI__Guru*** 125430 points

    Thanks for tracking that down, Mukul.  That should hopefully make it a bit more practical for d sandquist to use one of these timers to supplement the eCAP.

  • 0 in reply to Brad Griffis
    Prodigy 160 points

    If I'm using general purpose timers in 32-bit unchained mode:

    • I cannot use an external timer for timer3:4 no matter what1?
    • If I enter event capture, I can only use internal sources for the timers2?

    Is this true?

    1.TRM Figure 31-6. Dual 32-Bit Timers Unchained Mode Block Diagram. (Ch. 31.2.1.4.2.2 Unchained Mode)

    2.TRM section 31.2.1.4.2.2.5 Event Capture Mode (32-bit unchained General Purpose Counters)
    "Event Capture Mode is available only when the timer clock source is the internal timer (CLKSRC = 0) and the timer is in continuous mode (ENAMODE = 2h or 3h)."

  • 0 in reply to d sandquist
    TI__Guru** 116770 points

    Yes, both your statements are true. In 32 bit unchained mode the TIMER 3:4 always uses internal clock(PLL_AUXCLK) and the prescaler can only be programmed only to count the internal clocks cycles. Since the AUXCLK also driver the USB module you will need to use a clock 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz if you are using the USB module due to USB PHY requirements. The pre-scalar provide the flexibility to varying the time period after which the timer triggers an event.

    Event capture mode is available on the Timer 1:2 in 32bit unchained mode only when the clock source is internal and when it is configured in the continuous mode.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 160 points

    It's a shame that it appeared from the summary that this chip had up to 8 32-bit counters and capture registers that accepted external sources, but once I whittle down to specifics, there are none that work with an independent external clock & capture registers.
    Yes I could do it using gpio or internal clocks using interrupts or edma, but for my application I needed timers running off 4 separate external signals <100 kHz and capturing the count of theses via external pulse all in hardware.  Any reliance on interrupts or other method of counting risked unacceptable race conditions.

  • 0 in reply to d sandquist
    TI__Guru*** 125430 points

    Can you clarify on one point?  In particular, are you trying to get a "capture" (i.e. understand precise timing between pulses) or a "count" (accumulate number of events)?  Perhaps both -- if that's the case how many of each?  Perhaps there is still a way, but please provide more detail to help me understand the real requirements.

  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points

    The 45-55% duty cycle was intended for the case that you are truly trying to use an external time base for the timer.  For the scenario where you’re simply trying to count something only the “min” applies, i.e. it needs a little time to register a low or high level.

  • 0 in reply to Brad Griffis
    Prodigy 160 points

    Brad, I'd like to go offline to give more specifics.  I've contacted Taylor Busch asking if there is a way to work directly with you.