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AM1808 mDDR SRR

Kzk
Genius 5785 points
Other Parts Discussed in Thread: AM1808, OMAP-L138

Hello,

What's the certain initialization sequence command? I saw a phenomenon below. I seem that the mDDR is stuck in the SRR state. It's capable to recieve SRR command, but I don't want to use SRR command for the system reason. I'd like to know what command.

AM1808 Errata (SPRZ313G)
2.1.6 DDR2/mDDR Controller: mDDR Usage Note

Best regards,
Kazu

  • 0
    TI__Guru** 116100 points

    Hi Kazu,

    Are you testing this board for first time ?

    Are you using SRR command support DDR devices on your custom board ?

    Have your tried to have two consecutive initialization sequence for proper DDR init  after POR ?

    Could you please elaborate your requirement/problem/question to help you out

  • 0 in reply to Titusrathinaraj Stalin
    Genius 5785 points

    Hi Titus,

    There are two kinds of custom board. Its difference is mDDR types. I have to use these mDDR for supply surface. I want to commoditize software between mDDRs.

    The one is capable to receive SRR, the other one is not. It's fine to access mDDRs by CCS. But AIS boot has problem.

    The one which is capable to receive SRR is working if I check 'mDDR with SRR support’ option in AISgen. But it's not working if I un-check this option.

    I think this phenomenon is usage note in Errata. I'd like to know what command mDDR misinterpret.

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru* 84565 points

    Kazu-san

    The more indepth description on the usage note is as follows, 

    When first powered-on, the DDR2/mDDR controller on the OMAP-L138 sends DDR2 initialization sequences by default. If an mDDR memory is used on the board, the user application configures the IP to mDDR mode which then sends the mDDR initialization sequences. However it was found that certain mDDR memories  which implement the optional SRR command, can get locked up after the DDR2 init sequence.

     This is due to the MRS command to Mode Register 1 sent as part of DDR2 init. This command looks exactly like an SRR command for mDDR, and therefore the memory goes into the SRR state from which it does not emerge as no READ command is sent by the DDR2 init sequence as shown in the state diagram below. In this situation, the memory needs two back-to-back mDDR init sequences to correctly initialize it.

    ---

    Regards

    Mukul