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Accelerate IO buffer aging with OMAP L137

Louis Dupont
Intellectual 480 points

We recovered units based on the OMAP L137 (silicon rev. 2.1) which have been running 24/7 over the last 2 years. 5 out of the 6 recovered units appear to suffer from the OMAPL137, AM17x, C6747/5/3, DA83x/2x/1x/0x IO Buffer Premature Aging Assessment issue on the EMIFB clock pin (133MHz, 3.3V). The failure rate is much higher than what's specified in the silicon errata:

What could accelerate (ex: exposure to high/low temperature) this issue and explain that failure rate?

  • 0
    TI__Mastermind 43660 points

    Hello Louis,

    I believe the fail rate is estimated for the device which are operating as per the lifetime estimates given in the table.

    As you said, you are running the units 24/7 over 2 years, which is well beyond the lifetime estimates of the device. In this case, the failure rate may eventually increase.

    There is a workaround given in the errata SPRZ291I to increase the lifetime estimate as 2.2 years for 24/7 running. 

    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Intellectual 480 points

    Thanks Senthil,

    Those were just prototypes. We are not looking for a way to fix the issue with the 2.1 silicon revision but rather explain why we had such a high failure rate. Maybe it's my interpretation but given tha table above I would expect a failure rate of 0.5% for units running 24/7 over 2.1 years while we have a failure rate of 83% and probing the EMIB Clk output showed that the IO buffer was severely damaged even beyond what was documented by TI in some cases.

  • 0 in reply to Louis Dupont
    TI__Guru* 78285 points

    Hi Louis

    The table in the errata is provide some guidance as "examples" but there is additional variability on these rates based on customer use case. Usually the 2 things that we have seen speed up the failure rate is if the boards are running higher than nominal IO voltage or  if you are using both EMIFs (EMIFB and EMIFA) or EMIF and McASPs running 24/7 simultaneously. 

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Intellectual 480 points

    Thanks. Ideed we use EMIFA and EMIFB simulataneously. Do you have any documentation on speed up conditions? I've seen TI's workaround to lower the IO voltage but haven't seen anything regarding the simulataneous use of McASP or EMIFA interfaces.

  • 0 in reply to Louis Dupont
    TI__Guru* 78285 points

    Hi Louis

    Unfortunately there is no additional public data that I can share on the simultaneous use. As you can see these are broad market devices with varied use-cases and all such permutations cannot be comprehended or modeled. The examples provided in the errata provide guidance , but obviously cannot cover every scenario.

    The simultaneous EMIF scenario and higher then nominal IO were some use-cases we saw with other customers , so nothing I can share beyond the experience. 

    As long as you are sure that the failure signature matches what you see in the errata and wiki, I think it is the premature aging issue.

    Hope this helps.

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Intellectual 480 points

    The charts on p.9 provides the answer. Pass 2.1 years the failure rate grows exponentially. One should expect a failure rate of 83% roughly after 2.8 years.