Help from Mukul and Randy.

Hi Sinan
I am checking with the team assisting you on this the thread. Will see what we find out and get back to you.

Regards
Mukul

thanx for reply Mukul.

rwe are waiting your valuable helps urgently. thank you

Best Regards.

Sinan,

We have changed the code to disable the pull-up through SYSCFG1 module and tested the code in C6748 EVM board. We observe a stable data transmit signal on DX1 pin and it is synchronized to the FSX1

Please add the below code snippet in your main() function on the example path (C:\ti\biospsp_03_00_01_00\drivers\examples\evm6748\mcbsp\Master\src\mcbspSampleMaster_main.c)

1. Add the below include files in mcbspSampleMaster_main.c

#include <cslr/soc_C6748.h>
#include <cslr/cslr_syscfg1_C6748.h>

2. Append the new lines highlighted in "RED" on main() function in the same "mcbspSampleMaster_main.c" which would disable the pull-up resistor on the data transmit signal (DX1) and I believe, you will observe a stable data transmit signal (DX1) on the scope.

void main(Void)
{
CSL_Syscfg1RegsOvly syscfgRegs_1 = (CSL_Syscfg1RegsOvly)CSL_SYSCFG_1_REGS; 

LOG_printf(&trace,"Mcbsp Sample Application\n");

/* enable the pinmux for the mcbsp device */
configureMcbsp();

  syscfgRegs_1->PUPD_ENA = 0xFFFFFFFF; 
    syscfgRegs_1->PUPD_SEL = 0xC3FFFFFB;

return;
}

Note: In addition to the above code changes, you can also feed a constant value of 0x80 to buf[ ] content in "mcbspSampleMaster_io.c" and test it, you will observe a stable data transmit signal

Please test it on C6748 EVM if available and if not, check it on C6748 LCDK and I believe, you will see improvement in pull-up level coming down on LCDK board to some extent when you append the above fix, but on C6748 EVM, you would see a stable DX1 signal on the scope which nullifies the pull-up level to zero and you would see the issue gets fixed.

Kindly test it at your end and provide us the update on your observations.


Thanks & regards,
Sivaraj K

Hello Sinan,

Fix for the LCDK:

The McBSP_DX1 pin is multiplexed with GPIO0[1]. In LCDK, this pin was considered as GPIO and connected to SW1 and pull up (R257 - 5.6K) & pull down (R253 - 1K) resistor. Even when we control the internal pull to pull down through software, the external resistor over drive it and pulls the signal to undesired level.

We tried depopulating these external pull resistors (R257, R253) and checked the DX1 signal, it seems to be stable.

Regards,

Senthil

Hello Sinan,

Did you try this workaround and checked the data stability at your end ? could you please update on this.

Regards,
Senthil

Hello All,

Thanks for your assistance. Here is what we have done:

As in the message of Sivaraj (Jun 10, 2015 6:50 PM) we did the following changes on the example "mcbspSampleMaster"


void main(Void)
{
CSL_Syscfg1RegsOvly syscfgRegs_1 = (CSL_Syscfg1RegsOvly)CSL_SYSCFG_1_REGS;

LOG_printf(&trace,"Mcbsp Sample Application\n");

/* enable the pinmux for the mcbsp device */
configureMcbsp();

syscfgRegs_1->PUPD_ENA = 0xFFFFFFFF;
syscfgRegs_1->PUPD_SEL = 0xC3FFFFFB;

return;
}


Regarding Senthil's advice: Thank you Senthil. We had already done that for our LCDK .


As a result for the example "mcbspSampleMaster" we had a remarkable improvement on the stability of the DX1 signal.
But still there are "blinks" poping up (This is how I expressed it. Please see the scope video on the following link to understand what I mean): The data transmitted is a constant 0x80.
"drive.google.com/open;authuser=0"

We were not sure if those "blinks" are negligible (But we are sure that it is not a noise we pick up from the environment).
The reason we were dealing with this example was to go in steps as we were trying to figure out our actual problem with Anthony (e2e.ti.com/.../1501298).

Assuming that those "blinks" are negligible we carried on with our own actual problem where we externally generate the frame and clock signals.
So, in addition to the above changes in the "mcbspSampleMaster" example we have modified the program as follows:

Both the clock and frame signals are external.
clock is 2.048 MHz.
frame is synchronized with the clock and it is 8kHz.
We have 32 channels with 8 bits of words each.

Our modified example is on link "drive.google.com/open;authuser=0"

When we run our own modified example we observe the following DX1 signal on the scope:
Probe 1 is the frame signal.
Probe 2 is the DX1 signal.
"drive.google.com/open;authuser=0"
As seen on the above video we do not have stable DX1 signal.

For convenience here are the frame and clock signals:
Probe 1 is the frame signal.
Probe 2 is the clock signal.
"drive.google.com/open;authuser=0"
As seen on the video we have stable clock and frame signals.
And the timing of the clock and frame signals generated externally are adequate to the Figure 6-34 (McBSP timing) on SPRS590F.
The delay time of the frame signal to the clock signal is 40ns.

Consequently, we do not have a stable DX1 signal on our original setup. Returning to our original problem we are looking forward to your help.

Best regards.

Hi,

Thanks for your update.

In our C6748 LCDK setup standalone, we do not observe any blinks as you are reporting.

Could you please do a quick try on the code snippet below to completely disable the internal pull resistors (PUPD) & try the "mcbspSampleMaster" example code keeping internal framesync and clock in order to avoid blinks which you are reporting?

void main(Void)
{
CSL_Syscfg1RegsOvly syscfgRegs_1 = (CSL_Syscfg1RegsOvly)CSL_SYSCFG_1_REGS;

LOG_printf(&trace,"Mcbsp Sample Application\n");

/* enable the pinmux for the mcbsp device */
configureMcbsp();

syscfgRegs_1->PUPD_ENA = 0xFFFFFFFB; (disabling the complete internal PUPD resistor)
//syscfgRegs_1->PUPD_SEL = 0xC3FFFFFB;

return;
}

Kindly try the above code and let us know your observation on the scope. Please attach it as video sothat, it would be convenient for us to debug further if any.

Thanks & regards,
Sivaraj K

Below is the video shot of the new observation.
Still are the blinks.
"drive.google.com/.../edit"

Hi,

Are you using the clock setup for the TX section as below in your code?

Mcbsp_ClkSetup mcbspClkConfig =
{
Mcbsp_FsClkMode_INTERNAL,
96000, /* 96KHz */
Mcbsp_TxRxClkMode_INTERNAL,
Mcbsp_FsPol_ACTIVE_HIGH,
Mcbsp_ClkPol_RISING_EDGE
};

With the above configuration and completely disabling the internal PUPD resistor (syscfgRegs_1->PUPD_ENA = 0xFFFFFFFB) , we do not observe any blinks in our c6748 LCDK setup as like video shared by you. It looks strange for us but still, we will check more insignt on this.

Thanks & regards,
Sivaraj K

Yes, the clock setup for the TX section is as it is?

Hi,

With above configuration, we do not see such behaviour as you are reporting on c6748 LCDK, kindly check the attached video below:

https://www.sendspace.com/file/48bk12 (DX1 looks stable in the video)

Most probably, the blinks which you are observing should be carried over from other sources on your setup.

Thanks & regards,

Sivaraj K

Hi,

We have tested it on C6748 LCDK.

Hi sivaraj,

Could you send the board in you to us to test?

None of boards we bought run.

Best regards.

Sinan

Hi,

We will check and let you know the update on this.

Is your external pull down (R253 - 1K) resistor depopulated on your LCDK and the SW1 position kept at pull down?

Thanks & regards,
Sivaraj K