CC430F5137: cc430f5137 stopped working even after power reset

Hi,

I have at least  1 dozen cc430f5137 based on RF products stopped running after some hours and they won't run anyway even after power reset. Only after  re-programmed with the same codes again  then they can start work.

Depends on the saved value in a flash rom 0x1909 the software will chose one of  the different RF frequencies.

The main loop should be interrupted by either WDT (bmWUF_WOR) or external circuit (g_bWakeUpFlags).

The attached is captured infomation from debug tool.captured information by using the debug.doc

Below is part of the  software:

//InitRadio 
// Set the High-Power Mode Request Enable bit so LPM3 can be entered
// with active radio enabled 
PMMCTL0_H = 0xA5;
PMMCTL0_L |= PMMHPMRE_L; 
PMMCTL0_H = 0x00; 

// Set up SYNC WORD
WriteSingleReg(SYNC1, SYNC_WORD_MSB);
WriteSingleReg(SYNC0, SYNC_WORD_LSB); 

//------------------------------------------------------------------------------
/* MCU clock system (UCS) initialization
* - Start the 32768Hz crystal oscillator XT1
* - Configure the FLL to generate 8MHz clock using XT as reference
* - MCLK = SMCLK = 244 * fXT1 = 7.995392MHz from DCO/2.
*/
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 = SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.
UCSCTL6 = XT2OFF & msk_1 | //XT2 is off
XT1OFF & msk_1; // XT1 is Off

__bis_SR_register(SCG0); // disable FLL pulling of DCO
UCSCTL0 = 0x0000; // set DCO to lowest tap
// FLL loop divide-by-2, Fsys/Fxt1 ratio = 243+1 = 244
UCSCTL2 = FLLD__2 | 243; 
UCSCTL1 = DCORSEL_5; // good for 10..20MHz, we run Fdco = 16MHz and divide
// by 2 to make sure that clock duty cycle = 50% since
// we run at the 8MHz max limit for PMMCOREV = 0.
__bic_SR_register(SCG0); // re-enable FLL control
// maximum FLL settling delay = 1024 * f_MCLK / f_FLLREF
__delay_cycles(250000lu); 

bTimeout = 100; // try max 100ms
// wait for ALL oscillator fault flags to become clear
while (SFRIFG1 & OFIFG) 
{
__delay_cycles (8000lu); // delay ~1ms
// clear individual flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); 
SFRIFG1 &= ~OFIFG; // clear sum flag
if (--bTimeout == 0)
{
//something wrong
SOFTWARE_BOR_REBOOT 
} 
}
//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default) 
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;



.........

shippedcode =*((unsigned char *) 0x1909); 



//reset the PATABLE value
PATABLE_VAL = 0x50; // 0XC4-- 10 dBm;
// 0X50-- 0 dBm;
// 0X2D-- -6 dBm;
// 0X26-- -12dBm;
// 0x05-- -30dBm;
// 0xc0-- max 
//ResetRadioCore
// Strobes SRES -> sets radio in SLEEP mode
Strobe(RF_SRES);// Reset the Radio Core
Strobe(RF_SNOP);// Reset Radio Pointer

state = STATE_SLEEP; 

if(shippedcode ==1)
{
WriteRfSettings(&rfSettings_old); 
WriteSinglePATable(PATABLE_VAL); 
//change FIFO_THR back to 0x40
WriteSingleReg(PKTCTRL1, (rfSettings_old.fifothr & 0xF0)); 

oldcode();
}
else
{
WriteRfSettings(&rfSettings); 
WriteSinglePATable(PATABLE_VAL); 
//change FIFO_THR back to 0x40
WriteSingleReg(PKTCTRL1, (rfSettings.fifothr & 0xF0)); 

newcode();
}

.......

//=====================================================
// MAIN LOOP
//===================================================== 
while (1)
{
CLRWDT_16s

//===============================================
// Enter LPM3 sleep if no wake-up flag is pending
//=============================================== 
if (g_bWakeUpFlags == 0) // all wake-up flags clear, no radio active? 
{
if(Operating_mode ==IDLE) 
{
//make VLO (10khz) as ACLK's clock source
UCSCTL4 = SELA__VLOCLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;

LED_OFF

if (state != STATE_RX_WOR) 
{ 
Strobe(RF_SIDLE);
Strobe(RF_SFRX);
Strobe(RF_SFTX);
Strobe(RF_SCAL);
while ((Strobe(RF_SNOP) & 0xF0) != 0x00 );

state = STATE_RX_WOR;

//change FIFO_THR RX to 4
WriteSingleReg(PKTCTRL1, (rfSettings_old.fifothr & 0xF0)); 

// Set up 2 preamble bytes
WriteSingleReg(MDMCFG1, (rfSettings.mdmcfg1 & 0x8f)); 
// Set up 16 bit sync word (16/16)
WriteSingleReg(MDMCFG2, (rfSettings.mdmcfg2 & 0xf4) | 0x02); 

//what should happen when a packet has been received:
//RXOFF_mode and TXOFF_mode in IDLE
WriteSingleReg(MCSM1, 0x30);
// Disable CRC at end of packet
WriteSingleReg(PKTCTRL0, (rfSettings.pktctrl0 & ~0x04)); 
//disable appending RSSI and LQI info at the payload
WriteSingleReg(PKTCTRL1, (rfSettings.pktctrl1 & 0xFB));

WriteSingleReg(PKTLEN, 2); // Set up packet length 
}

Strobe(RF_SIDLE); 
Strobe(RF_SPWD); //turn off RF 

T_WOR_1s =2; //0.125s
WDTCTL =WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL_2+WDTIS1; //1/16s 
SFRIE1 |= WDTIE; // Enable WDT interrupt 
__bis_SR_register(LPM3_bits + GIE); //enter LPM3 and re-enable interrupts
// CPU SLEEPS HERE!
__delay_cycles (800ul); //waiting 
SFRIE1 &= ~WDTIE; // disable WDT interrupt 
//ACLK = XT1 (default), SMCLK = DCOCLKDIV (default), MCLK = DCOCLKDIV (default) 
UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV; 
//delay_cycles(x) is stopping in the code and waiting for x MCLK cycles 
} 
}

//==========================================
// Handle pending wake-up flags
//==========================================
CLRWDT_16s 
if (g_bWakeUpFlags & bmWUF_WOR)
{ 
CLRWDT_16s;

RF1AIE |= (BIT9 + BIT1); // Enable the interrupt
RF1AIFG &= ~(BIT9 + BIT1); 
RF1AIES |= BIT9; // Falling edge of RFIFG9pt

Strobe(RF_SRX);

__delay_cycles (16000ul); //waiting for 1.8ms

// the followings are to check g_bWakeUpFlags

.........

Thanks,

Derong Yuan