• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 1170 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP-L138: Questions about ECC of NAND Flash

Masato Miyashiro
Expert 1500 points
Part Number: OMAP-L138

Hi,

I was asked by OMAP-L138 from my customer.
Please tell me about the read sequence of "20.2.5.6.6.2 4-Bit ECC" in the Technical Reference Manual.


1. What is the reason why the dummy lead of Step 10 was added by the revision of Rev. A -> Rev. B?

> 10. Perform a dummy read to any EMIFA registers except the
> NAND Flash error address 1-2 registers
> (NANDERRADD [2: 1]) or the NAND Flash error value 1-2
> Registers (NANDERRVAL [2: 1]).

  Also, what will happen if we do not do this?

2. Is Step 10 necessary also when not carrying out the processing of Step 11 at this point?

3. If Step 10/11 is not executed, is the first NANDFSR read in Step 12 treated as a dummy read,
   and the read value may become undefined?
  (1 to 3 are returned to ECC_STATE although the calculation processing is not completed)

I am sorry that the question is difficult to understand.
I would appreciate it if you can answer.


Best Regards,
Miyashiro

  • 0
    TI__Guru**** 161600 points
    Hi,

    Let me have a look at this and I will update the thread.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1500 points
    Hi Yordan,

    Do you have any update on this issue?

    Best Regards,
    Miyashiro
  • 0
    TI__Guru** 116170 points
    The dummy read was added to the TRM to avoid a possible race condition that may occur when accessing EMIF registers. Refer to usage note: 2.3.4 in the device errata as there is an errata for EMIF in Extended Wait State that also recommends adding this dummy read command.

    www.ti.com/.../sprz301m.pdf

    Older TI software that we provided for this device, didn`t implement this dummy read but based on feedback from some customers and internal testing we added this step in the sequence for additional safety. You will need to evaluate how critical it is to avoid this race condition in your product

    We don`t have complete details of not implementing this dummy read specific to NANDFSR as this will depend on timing of the read in your software and the state in which the ECC state machine is in when the core reads the register.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Expert 1500 points
    Hi Rahul,

    Thank you for your reply and explaining in detail.

    I will answer your answer to my customer.
    Please let me rely again if something is asked additionally.

    Best Regards,
    Miyashiro