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OMAP-L138: Unstable uPP DMA transfer

Karel Szurman
Prodigy 140 points

Part Number: OMAP-L138

Our application is programming uPPA and uPPB channels to receive periodically blocks of 4096 samples @ 1 msec rate.

The uPP configuration is dual channel Rx mode, 8-bit mode for uPPA, 16-bit mode for uPPB, Enable and Start signals enabled, Wait signal omitted, Clock signal is continuously generated by FPGA.

Even though the uPP peripheral was initialized following the step-by-step procedure described in the TI reference manual, unstable DMA transfers are observed over reset cycles such as either missing DMA transfer for one or both channels, or DMA transfer not synchronized between channels.

Is there any known issue on that topic?  What kind of help TI can provide to help debugging the issue?

We found question related to providing uPP clocks during initialization sequence in https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/372349?tisearch=e2e-sitesearch&keymatch=upp%20clock

Could missing uPP clock signal during initialization cause similar issues to ours? (i.e unstable DMA transfers)

Note that we perform initialization of uPP peripheral according to step-by-step procedure (steps 1-7) during an application startup and programming of DMA transfer (steps 8-10) in the end of startup when everything should be prepared to start uPP receiving. 

  • 0
    TI__Guru**** 161600 points
    Hi,

    Which SDk are you using?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 140 points
    Hi Yordan,
    we don't use any SDK. we have developed our own drivers for all peripherals.

    Karel
  • 0
    TI__Guru* 86265 points

    Hi Karel
    Do you have more data from your test and observations?

    1) What is clock speed from the FPGA? Do you have the ability to lower the clock to see if failures still exist?
    2) Please further clarify what you meant here "unstable DMA transfers are observed over reset cycles such as either missing DMA transfer for one or both channels, or DMA transfer not synchronized between channels."
    Is the failure only happening when you try the test with reset/restarting the application, does it fail every time or sporadically during this reset test?

    3) You said
    >>could missing uPP clock signal during initialization cause similar issues to ours? (i.e unstable DMA transfers)




    Can you elaborate here, so is the the Step 2 for you that the module clock via PSC is enabled, but the transmit clocks that are sourced by the fPGA not on at this time? Can you change this to try if this makes a difference?

    Regards
    Mukul 

  • 0 in reply to Mukul Bhatnagar
    TI__Guru* 86265 points
    Hi Karel
    This thread got locked because there was no activity.
    I am marking this as "TI thinks resolved" for easier track-ability.
    I know there is a new thread that you have started on this here
    e2e.ti.com/.../670687

    We will continue to work with you on supporting it on the new forum post.

    Regards
    Mukul