Watchdog in OMAP-L138

Alexey,

A few questions for you:

Can you confirm that the timer is using the internal clock?
Have you tried performing a system/cpu reset?
How are you servicing the watchdog system interrupt?

There is an L-137 example that uses the timer as a watchdog available here: http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL

The example source code may be beneficial to look at and compare to your source code.

-Kevin

Alexey,

Your sequence initiated a reset on my device.  Can you verify that the SYSCFG[SUSPSRC] setting for TIMER1 is set to the appropriate CPU?

If that is ok, can you verify that 0x0B shows up in TGCR immediately after you write it?  Also, try to initialize the TMR12/TMR34 values to zero before you write the PRD12 value.

-Tommy

Thank you for the reply.

I can see that the TGCR gets 0x0A after writing 0x0B into it. I will verify the SUSPSRC register setting, but as I understand, this register related to the emulation mode (debugger) and I was also trying to use this sequence without debugger at all and it still did not work.

Thanks, Alexey.

Tommy,

Thank you for the example, it works!

I think that my problem was the other timer registers that I did not clear before trying to use WD.

Alexey.

Thanks Tommy,the problem has confused me a few days and now by using the example,the WDT works!