boot issue on custom DM8148 board

Shunnian Zhai,

Did you checked your boot Switch configurations,if any?
Refer the user guide for your H/W. it should tel you how to configure the switches for different boot modes(SD/uart/nand etc.).

hi, ravikiran,

yes, bootmode in our board sets to 11101 [0_4], nand-sd-uart all supported. this setting is already tested in evk, no problem.

any other idea?

thanks,

shunnian

ravikiran hv said:

Shunnian Zhai,

Did you checked your boot Switch configurations,if any?
Refer the user guide for your H/W. it should tel you how to configure the switches for different boot modes(SD/uart/nand etc.).

First compare your board with the EVM, and check if your uboot has adjusted for those difference.

For example, if you only use EMIF0 instead of both, you need adjust your DMM LISA registers

Hi, Biser,

Firstly, thank you for your reply.

I have done the modification on DMM LISA map and EMIF initialization based on our board since we only use EMIF0 and disable EMIF1.

My understanding is that U-Boot-min is running at internal SRAM. So, to exclude the impact of DDR3 initialization code and make sure that U-Boot-Min runs to output some debug messages, I did the following changes in file Ti8148_evm.h:

1) uncomment this to prevent from calling config_ti814x_ddr() in s_init()
//# define CONFIG_TI814X_CONFIG_DDR

2) Add this to skip the u-boot relocate to DDR3

#define CONFIG_SKIP_RELOCATE_UBOOT

However, this issue is still same: no output from UART. I am suspecting that U-Boot-Min code is hanging somewhere during initialization? Any suggestion to debug this issue? Usually, how do you debug U-Boot-min initialization code? is there any tool to use?

Thanks and Regards,

Shunnian

Hi, Hongfeng,

Thanks for your reply. I have done the change on LISA map since we only use EMIF0.

Please advise if there are any other area I need to change? Please check my reply to Biser above to see what I have done so far. Since u-boot-min is running at internal ram, my first target is to make it run to output some debug message via UART.

Regards,

Shunnian

Have you checked your pin mux registers? (mux.h)

Are you using a different UART?]

If you don't have NAND or NOR flash, you can remove those code as well.

If you have JTAG access, it's always much easier just following the code with emulator, to see where the code stops.

Hi, Hong Feng,

I have resolved this issue. The main cause is due to our DDR3 problem. Now U-Boot can boot-up without any problem. However, I encounter another problem: when loading kernel, it always stops inside start_kernel function as following message.

---------------------------------------------------------------------
305 bytes read
Running bootscript from MMC/SD to set the ENV...
## Executing script at 80900000
reading uImage

2280016 bytes read
## Booting kernel from Legacy Image at 80009000 ...
Image Name: Linux-2.6.37
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2279952 Bytes = 2.2 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
start_kernel...enter

---------------------------------------------------

After this point, kernel hangs. No further output. Any idea what is wrong here?

You mentioned that it can debug the issue with JTAG access. I want to know how to do it. Any document on this area?

Thanks,

Shunnian

Hi, Hong Feng,

The issue is resolved today. Anyway, if you have doc on how to use jtag to debug u-boot and kernel, please let me know.

Thanks,

Shunnian

Hi, Biser,

I have resolved the issue. When setting DDR3 clock in our board at 400MHz, it has problem. When I change to 100/200MHz, it works file.

Now I want to follow the DDR initialization procedures you suggested. However, when I run the program, I got the error as follows:

RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
WR DATA RATIO MAXIMUM VALUE DIDN'T CONVERGE
WR DATA RATIO MINIMUM VALUE DIDN'T CONVERGE
*********************************************************
Byte level Slave Ratio Search Program Values
*********************************************************
BYTE3 BYTE2 BYTE1 BYTE0
*********************************************************
Read DQS MAX 0 0 0 0
Read DQS MIN 0 0 33 0
Read DQS OPT 0 0 80000019 0
*********************************************************
Read DQS GATE MAX 0 0 0 0
Read DQS GATE MIN 0 0 0 0
Read DQS GATE OPT 0 0 0 0
*********************************************************
Write DQS MAX 0 0 0 0
Write DQS MIN 0 0 0 0
Write DQS OPT 0 0 0 0
*********************************************************
Write DATA MAX 0 0 0 0
Write DATA MIN 0 0 0 0
Write DATA OPT 0 0 0 0
*********************************************************

===== END OF TEST =====

Please advise what may be wrong?

Thanks and Regards,

Shunnian

For debug of linux kernel with CCS pls refer http://processors.wiki.ti.com/index.php/Linux_Debug_in_CCSv5

For debug of uboot , run uboot, connect to A8 core and load symbols of uboot binary.After this you will be able to debug as usual.

Hi, Biser,

Yes, I followed the steps described in the wiki page. Maybe it is because our board currently cannot run at 400MHz DDR3 speed and only 100/200MHz works. Maybe I should try to modify the .GEL file to configure the DDR3 to 200MHz, but not sure if it is root cause for the error. Please advise!

Thanks,

Shunnian

Hi, Badri,

Thank you for your information. I will try it when I have time.

Regards,

Shunnian

hi, i meet the same problem.

However, when i change the ddr3 clock to 200Mhz, the problem still exist .

And I cann't connect the device through jtag again. It stuckes in the following step when jtag start to config the ddr pll.

while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000600) != 0x00000600);

The uboot ddr clock that I change is:
../arch-ti81xx/clock_ti814x.h
#define DDR_M (pg_val_ti814x(400, 400))             //#define DDR_M (pg_val_ti814x(800, 800))

please help me, thanks.

PS: do you have QQ or else.

Hi, John,

You can try to build u-boot.min.uart to run u-boot.min inside SDRM first, don't init DDR for now by doing the followings:

1) modify makefile line 3217:

old->
        echo "TEXT_BASE = 0x80700000" >> $(obj)board/ti/ti8148/config.tmp; \

new->
        echo "TEXT_BASE = 0x40310000" >> $(obj)board/ti/ti8148/config.tmp; \

2) uncommnet the following line (line 42) in ti8148_evm.h

//# define CONFIG_TI814X_CONFIG_DDR

3) follow the instruction in u-boot user guide to download the u-boot.min.uart to your target board.

This should make your board run into the u-boot-min.

Hope this works for you. Good luck!

Regards,

Shunnian

Hi Shunnian,

Thanks for your reply.

After i change the ddr3 regs value, the uboot.min works now.

However, the board stops in the starting the second uboot.

U-Boot 2010.06 (Feb 27 2013 - 14:20:37) DM8127_IPNC_3.20.00

TI8148-GP rev 2.1

ARM clk: 600MHz
DDR clk: 400MHz
L3 clk: 200MHz
IVA clk: 450MHz
ISS clk: 400MHz
DSP Default OFF
DSS Default OFF

DRAM:  1 GiB
NAND:  HW ECC BCH8 Selected
256 MiB
Using default environment

The 2nd stage U-Boot will now be auto-loaded
Please do not interrupt the countdown till TI8148_EVM prompt if 2nd stage is already flashed
Hit any key to stop autoboot:  0

NAND read: device 0 offset 0x20000, size 0x40000
 262144 bytes read: OK
## Starting application at 0x81000000 ...

the board stops in the "Starting application at 0x81000000 ". This is very strange. Do you know why?

Thanks!

Hi, John,

Have you tried to boot from SD?

Also, you can try to do memory test in u-boot.min by running "mtest ..." to make sure the DDR work properly.

Regards,

Shunnian

Hi Shunnian

               I have the same problem.We have 9PCS board,and 3PCS have the problem.And others OK.

               We try to boot from UART,and it doesnt work.

              Is it DDR3's problem?

             I have test the DDR data,there is no data.

             thks!

Hi, Li Lin,

What is your issue? Cannot boot from u-boot.min? For my case, it is DDR3 HW related issue and all board cannot work. So, I reduce the speed to 200MHz then it works.

What DDR3 speed are you running?

Regards,

Shunnian

Hi Shunnian

             We have 9PCS boards all, and 3PCS can not boot from u-boot.min. Our DDR3 speed runs at 400MHz.And we also use u-boot.min.uart,it doesnt work normally.

            I think it is HW problem,because there is no DDR3 DATA when boot. We will try to reduce the DDR3 speed.

            But there is another question,why are some boards OK,and some NG?

            By the way,we have the problem only on V2.0 boards. We have 10PCS V1.0 boards that all dont have this problem.

           We dont change DDR3's PCB and SCH from V1.0 to V2.0.

          Do you have any other advice?

         THKS!

I am struggling with the same issue now.

First batch of boards all worked fine up to 533Mhz DDR3 clock, the second batch only 1 out of 4 can run at 400Mhz, other three can run at reduced clock speed.

The only thing we changed in 2nd batch is DM8148 silicon version, which is changed to 3.0 from 2.1

Are they the DDR3 Problem? Do you try to change the DDR3? Or it is the PCB problem. Now, we can not find the problem.We will try to do the following steps:

1) reduced clock speed

2)change the ddr3

@lilin: I figured out the cause of DDR3 issue. The solder paste was exposed too long after printed. We built another batch of board, so far at least the ddr3 part is working fine.

Hi All,

We are also facing the same issue.   3/10 birds are not working in our 2nd batch.  First batch was a real success where all boards 10/10 were working since last 2 -3 months. 

Can someone guide us to test ddr3 @ 200mhz from internal RAM?

Where should I change to test it at such a lower freq?

Re

regards,

Kartik

Hi Biser,

The DDR initialization procedures at:  http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

It requires JTAG connection to 8148. Is there any other approach to get the optimal values whitout JTAG connection?

I can not connect to 8148 through JTAG.

Hi,

I followed the instruction of skipping ddr for u-boot MIN, but it still hangs.
I think it might be because If we're moving from first 64k to the next 64k of SRAM,while u-boot.min.uart size is in my compilation is 68616 (>64k), it probably can explain why it fails in my system, right ? I wonder how it worked in other compilations....
Anyway, how can I be sure it is issue of DDR ?

Thanks for any idea,
Ran

Hello,

Can someone please attach min.uart version which skip ddr configuration and continues in RAM, so that I can verify that this is a DDR issue ?

Thanks

Ran

I have met the sanme problem. After setting the speed of DDR3 to 200MHz, it's done.