Enabling L1D cache on EVM6424

KrzysztofCh

My question is how to enable L1D cache. I am running simple task in DSP/BIOS on EVM6424. In TCF file i defined sizes of L1P, L1D cache. I'm measuring performance of a function using STS object. The function, which is being measured, is using one look up table in many interations.

What I expect is that L1D should boost function performance since after first iteration look-up-table should stay in cache (it's only 256 bytes so there is no cache size problem and this function is only task in OS so there is nothing else to overwrite cache).

I can see that L1P cache is working because performance depends highly on L1P settings in TCF file but it is completly independent of L1P settings in TCF file.

Krzysztof

over 16 years ago

Brad Griffis over 16 years ago

TI__Guru*** 125430 points

This is a pretty typical question so I created a more in-depth wiki article here:

http://wiki.davincidsp.com/index.php?title=Enabling_64x%2B_Cache

I'll try to post some screenshots from BIOS to help a little more.

Is your data stored in DDR? Is your code/data in DDR (external)? If so, then it's probably the MAR bits that are causing your problem. Code in DDR gets cached in L1P regardless of the MAR bits whereas data is dependent on the MAR configuration.

Brad

Brad Griffis over 16 years ago in reply to Brad Griffis

TI__Guru*** 125430 points

OK, I added the screenshots to the wiki page. I'm pretty sure the MAR bits are your issue. I noticed they are not set by default. I will raise this issue with the BIOS team separately to see why they are not setting those bits by default.

Brad

KrzysztofCh over 16 years ago in reply to Brad Griffis

Prodigy 140 points

But the thing is that I keep my application and data in IRAM (which is L2 SRAM as i believe) so as you said it should be cacheable independent from MAR bits. So if I use in my function 256bytes of data I should expirience at least slight improvement when L1D is set higher than 0k but STS object gives the same result for L1D=0k and L1D=32k.

Brad Griffis over 16 years ago in reply to KrzysztofCh

TI__Guru*** 125430 points

Is this on hardware or in a simulator? I agree there should be a significant difference between the two cases. Perhaps you could look at the L1DCFG register in the memory window. It's a 32-bit register at address 0184 0040h. That will tell us if the cache is being configured properly.

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Enabling L1D cache on EVM6424