Hi All
Please may someone help out with my current situation. I have an application running on a C6424 & DSP BIOS, that uses a ping pong buffering scheme and the EDMA3 controller to service the McBSP0 (Tx and Rx). All executes well until HPI/EMIF is exercised. The peripherals are configured as follows (Refer to attachment for source code snippets).
McBSP0 Rx and Tx clock and frame sync are all generated from an external source, hence sample rate generator is disabled. RINT and XINT are used to signal RSYNCERROR and XSYNCERROR respectively.
McBSP and EDMA synchronisation occurs through XEVT and REVT.
EDMA3 configured to use a ping pong buffer scheme for Tx and Rx, One QDMA channel is configured but idle when the failure occurs. A dedicated HWI is used to service ping/pong transfer completions. All EDMA events are enabled on shadow region 0, QDMA events on shadow region 1
The cache is enabled and SCR priorities have been re-configured accordingly. (Refer to attachment for new priorities)
The system starts up correctly and operates with no failures indefinitely. At a later stage the HPI and EMIF are loaded which results in the EDMA3/McBSP0 hanging. It looks like either REVT from the McBSP does not trigger or the EDMA3 misses REVT and all processing of data on the interface stops. Manually resetting the transmitter and receiver on McBSP0 (by writing to SPCR bit 0 and bit 16 through Code Composer) rectifies the failure in most instances. Viewing all McBSP0 and EDMA3CC/TC0 registers reveal no error flags during failure.
The only anomaly I can see is that McBSP0 SPCR shows RRDY = 1, RFULL = 1 (understandable as EDMA3 is not reading from DRR) but RSYNCERROR = 0. I would have expected this to be 1 given the state of McBSP0.
Any ideas or any extra info needed?
Thanks
Nick
