cache state verification

Hi Elad,

Thanks for your post.

May be, you shall try issuing the appropriate CSL commands to configure the L1P, L1D & L2 cache size and can be enabled in the program code as follows:

CACHE_L1pSetSize();

CACHE_L1dSetSize();

CACHE_L2SetSize();

You have privilege to control whether the external memory addresses are cacheable (being stored in L1D or L2 cache) or non-cacheable through Memory attribute register (MAR) bits (0 = noncacheable, 1 = cacheable). The memory attribute registers are documented in TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). You shall enable caching for the external memory through CSL function CACHE_enableCaching. For more details. please refer Section 2.3 in the c674x cache user guide doc. as mentioned below:

Yes, you are right, if you increase the L2 Cache size, the memory will be taken from higher memory addresses which is SRAM. May be, you shall check all possible cache configurations for C674x devices with 2048K bytes of L2 memory in Figure 2-1 of Section 2.3 in the c674x DSP cache user guide as given below:

http://www.ti.com/lit/ug/sprug82a/sprug82a.pdf

Also, please check sections 2.1 & 2.2 for configuring L1 & L2 Caches and also some examples 2-1 & 2-2 in the above doc.

Please check Section 3 for optimizing the cache performance in the above doc. and you will get a better idea on the same.

Thanks & Regards,

Sivaraj K