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Tiva C Series TM4C123GH6PM ADC - Processor Trigger with Trigger_Always not working correctly

Hello,

I am trying to write some code that should use one ADC module with each sequencer configured differently.   I have SS1 and SS2 configured for Proccessor Triggering.  I use SS3 with Trigger Always to send samples to the digital comparator which is set to interrupt with hysteresis once mode.  The priorities are 0,1,3 for SS1, SS2, and SS3 respectively. Each module works independently but together they do not function as expected. 

Here is the initialization for each of the sample sequencers.

// Allow register access to ADC0 and ADC1
SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC0);
SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC1);

// Configure all of the pins on the ADC's for ADC Type
GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_4);
GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_5);

GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0);
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_1);
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2);
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_3);

GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_4);
GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_5);

// Configure all of the pins for the IR Emitters
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_6 | GPIO_PIN_7);
GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6);
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_4);

/**
* Enable Sample Sequencer 1 on ADC0
*
* This Sample Sequencer will be used to sample the SIDE_1_IR receivers
* We will sample the LEFT_FRONT first (PD2 - CH5) and then sample
* the RIGHT_BACK (PB5 - CH11)
*
*/
ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_PROCESSOR, 0);
ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH5);
ADCSequenceStepConfigure(ADC0_BASE, 1, 1, ADC_CTL_CH11|ADC_CTL_END | ADC_CTL_IE);
ADCSequenceEnable(ADC0_BASE, 1);
//ADCHardwareOversampleConfigure(ADC0_BASE, 8);


/**
* Enable Sample Sequencer 2 on ADC0
*
* This Sample Sequencer will be used to sample the SIDE_2_IR receivers
* We will sample the RIGHT_FRONT first (PB4 - CH10) and then sample
* the LEFT_BACK (PD3 - CH4)
*
*/
ADCSequenceConfigure(ADC0_BASE, 2, ADC_TRIGGER_PROCESSOR, 1);
ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH10);
ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH4|ADC_CTL_END | ADC_CTL_IE);
ADCSequenceEnable(ADC0_BASE, 2);

SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC0 );
SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC1 );

// Select the analog ADC function for these pins.
GPIOPinTypeADC( GPIO_PORTE_BASE, GPIO_PIN_0); //CH3 - Right Encoder B
GPIOPinTypeADC( GPIO_PORTE_BASE, GPIO_PIN_1); //CH2 - Right Encoder A
GPIOPinTypeADC( GPIO_PORTE_BASE, GPIO_PIN_2); //CH1 - Left Encoder B
GPIOPinTypeADC( GPIO_PORTE_BASE, GPIO_PIN_3); //CH0 - Left Encoder A

/**
* Set up ADC1 sequence 1 for operation for the encoders
*
* Uses Comparator 0 and 1 to check for rising edge
*
* CH0 - PE3 - Left Encoder A
*
*/
ADCSequenceConfigure(ADC1_BASE, 1, ADC_TRIGGER_ALWAYS, 3);
ADCSequenceStepConfigure(ADC1_BASE, 1, 0, ADC_CTL_CH0|ADC_CTL_CMP0);
ADCSequenceStepConfigure(ADC1_BASE, 1, 1, ADC_CTL_CH0|ADC_CTL_END);
ADCSequenceEnable(ADC1_BASE, 1);

//Set up the comparator for Left Encoder A
ADCComparatorConfigure(ADC1_BASE, 0, ADC_COMP_TRIG_NONE|ADC_COMP_INT_HIGH_HONCE );
ADCComparatorRegionSet(ADC1_BASE, 0, ENCODER_MAX_LOW, ENCODER_MAX_HIGH);
ADCComparatorReset(ADC1_BASE, 0, true, true);
ADCComparatorIntEnable(ADC1_BASE, 1);

// Set up Hardware Interrupt for ADC
Hwi_Params_init(&left_encoder_hwi_params);
//encoder_hwi_params.arg = (UArg)adc_hwi;
Hwi_construct(&left_encoder_hwi, INT_ADC1SS1, left_encoder_count, &left_encoder_hwi_params, NULL);

/**
* Set up ADC1 sequence 1 for operation for the encoders
*
* Uses Comparator 0 and 1 to check for rising edge
*
* CH2 - PE1 - Right Encoder A
*
*/
ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_ALWAYS, 3);
ADCSequenceStepConfigure(ADC0_BASE, 3, 0, ADC_CTL_CH2|ADC_CTL_CMP0);
ADCSequenceStepConfigure(ADC0_BASE, 3, 1, ADC_CTL_CH2|ADC_CTL_END);
ADCSequenceEnable(ADC0_BASE, 3);

//Set up the comparator for Right Encoder A
ADCComparatorConfigure(ADC0_BASE, 0, ADC_COMP_TRIG_NONE|ADC_COMP_INT_HIGH_HONCE );
ADCComparatorRegionSet(ADC0_BASE, 0, ENCODER_MAX_LOW, ENCODER_MAX_HIGH);
ADCComparatorReset(ADC0_BASE, 0, true, true);
ADCComparatorIntEnable(ADC0_BASE, 3);

// Set up Hardware Interrupt for ADC
Hwi_Params_init(&right_encoder_hwi_params);
//encoder_hwi_params.arg = (UArg)adc_hwi;
Hwi_construct(&right_encoder_hwi, INT_ADC0SS3, right_encoder_count, &right_encoder_hwi_params, NULL);

SS3 is configured to simply call ISR and does so successfully.

The problem is in a task that has the following code.  I get stuck in the while loop indicating that the sample sequence is never completing. 

// Trigger ADC0 SS1
ADCProcessorTrigger(ADC0_BASE, 1);

// Wait until the sample sequence has completed.
while(!ADCIntStatus(ADC0_BASE, 1, false))
{
}

ADCIntClear(ADC0_BASE, 1);

I have tried many different things attempting to get this to work.  I also read that in the Errata, there are some priority mistakes for the ADCs.  I have tried to alter the priorities to see if that was what was happening.  The wording was a little difficult to follow but I believe I should not have the problem explained. 

Any help would be greatly appreciated. 

Thank you,

Anthony 

  • Hello Anthony,

    Is the code stuck in this loop or is it stuck in the ISR for SS3? Did you check the ADC#03 Errata for SS3?

    Regards

    Amit

  • Amit,

    It isn't stuck in the ISR.  It will still enter and exit the ISR for SS3, but the while loop never continues.  To me that means that SS1 never actually completes.

    I'm not sure which errata that is. Do you have a link? I've tried searching for it but the errata I did find only talked about the priority issue.

    Thanks,

    Anthony

  • Hello Anthony,

    The errata link for TM4C123 (See the errata marked ADC#03)

    http://www.ti.com/lit/pdf/spmz849

    Now instead of using Always Trigger for SS3, if you change it to SS2 and follow the errata guidelines, it should work.

    Regards

    Amit

  • Amit,

    I did not see the last sentence before about SS3.  Can you expand upon that note? Is that saying that I can only use one step of SS3 with all configurations? Or is that saying I can only use one step WITH the digital comparator configuration?  I really hope it's the latter.

    Thanks a lot for your help,

    Anthony

  • Hello Anthony

    It means that you need a dummy channel mapping after the digital comparator input channel

    Since, SS3 has only one channel, you would need to use SS2 with one channel for the digital comparator and another channel as a dummy channel which will never match any data.

    Regards

    Amit

  • Amit,

    It was completely my mistake.  When I read the datasheet I mixed up the FIFO depth of SS0 and SS3.  I was intending to use the one with a depth of 8 and end it early as I was aware that I needed the dummy step that the depth of 1 would not provide.  I changed to SS0 and it works as expected.

    Thank you,

    Anthony

  • You are not alone in that mis-step.  Sequence 0 supports 8 conversions, higher numbered Sequence 3 just one - this unnaturalness adds uncertainty. 

    A labeling of SS0_8, SS1/2_4, & SS3_1 encapsulates the channel size - guardbands against misuse...