McBSP - UART issues on C6713

Aditi,

1) You are correct that the divider only goes to the value 255, which represents a divide by 256 (CLKDV+1). This controls the lowest baud rate that can be achieved with the internal clock source. You have the option to supply to the CLKS pin an external clock source that runs much slower than the DSP clock. This could allow the lower baud rate that you want.

2) Start with the exact code in the example and get it running before making changes, such as INT13 instead of INT14.

Try using the second method, with GPIOs. This should be very effective with your low baud rate and would not require an external clock source.

Regards,
RandyP

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Randy,

I am trying to use the GPIO code as you suggested.

I am not able to find the MCBSP_DX_IO_H, MCBSP_DX_IO_L and MCBSP_DRSTAT macros used in the code.

Can you point me where to find the macro information? ASAP please.

Thanks,

Aditi

Aditi,

What example files have you downloaded? These macros are in SoftUart.h, but I do not know if these files are part of what you are using.

Was that ASAP enough? :)

Regards,
RandyP

Randy,

Thank you for the reply. I really appreciate it.

I have taken the code from the SPRA633C document. I did not find SoftUart.h.

For time being, I just wrote he macro for MCBSP_DRSTAT. If you can point me to the SoftUart.h file that will be really helpful.

Also one more question. I want the UART code (a function) to be run by BIOS.

How do I add it to the BIOS scheduler? Because there are no interrupts, how do I do it?

This is what I want to acheive

1) The BIOS constantly runs the code to find UartSpeed to find if there is any activity on the Rx pins (how can this be added to the BIOS scheduler)

2) If the UartSpeed is non-zero, then it calls the function to find the input character. (this could be done as a SWI_post I believe)

3) Based on what the input char is it has to send some data out (this also goes into the SWI_post function).

Thanks,

Aditi

Aditi,

The files that I found are not related to this application note, and I did not write them. The macros are

#define MCBSP_BASE(x)            (0x018C0000 | (x * 0x40000))
#define PCR(x)                    ((volatile int *)(MCBSP_BASE(x) | 0x24))
#define SPCR(x)                    ((volatile int *)(MCBSP_BASE(x) | 0x08))
#define MCBSP_DRSTAT(x)            ((*PCR(x) >> 4) & 1)
#define MCBSP_IO_ENABLE(x)        ((*SPCR(x) &= 0xfffefffe)); \
                                ((*PCR(x)  |= 0x00003000))
#define MCBSP_DX_IO_H(x)        ((*PCR(x)  |= 0x00000020))
#define MCBSP_DX_IO_L(x)        ((*PCR(x)  &= 0xffffffdf))

The code described in the SPRA633 application note is not going to fit easily into a BIOS scheduler.

Please look through the training information available on the TI Wiki Pages. Search for C6000 Workshop, and start with the C6000 Embedded Design Workshop Using BIOS. This will help you if you are looking for a better understanding of DSP/BIOS.

The application note does an excellent job of demonstrating a technique that could be used. The methods here may not be practical for your system. Or you may be able to apply your engineering skills to develop another method that might fit better with DSP/BIOS and your overall application.

Regards,
RandyP

Randy,

Can you suggest me a way to get an interrupt sort of thing to the DSP or adding some sort of task or somehting

that triggers the DSP everytime there is some activity on the UART Rx line.

One of my thoughts was to tie the DR (McBSP as GPIO) and one of the EXT_INT (configured to be triggered on falling edge)

lines together so that I can get an interrupt whenever the Rx line goes low. But the problem is the DSP is triggered on every low going edge

that is not needed. We only need to interrupt on the START word of the UART and ignore the rest of the low going edges in the word.

This is the only way (McBSP as GPIO) to make the UART work because of some hardware limitations I have on the board.

So I need to find some way to get this to work.

Thanks,

Aditi.

Aditi,

With your plan to tie DR and EXT_INTn, you could turn off the interrupt from EXT_INTn if you do not want to generate that interrupt for a while. After the serial byte is received, then you can turn it back on.

You could also change the polarity of the EXT_INTn interrupt so you get interrupted on the next rising edge and read a timer to determine how long the interval is between the falling edge and the next rising edge.

Any interrupt-driven method like this could require some noise filtering or extra sampling to ignore short noise spikes on the DR/EXT_INTn line.

In addition, you could setup a timer from that first edge and use that timer to count off P/2 and P shown in Figure 13 of SPRA633C. The timer could cause an interrupt which then gives you a way to avoid pure polling of the DR input.

Regards,
RandyP

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Randy,

As suggested, I have tried to tie the DR and EXT_INT6 together.

Also set up the ISR, configured the polarity of the interrupt as needed.

In the ISR, I disable the EXT_INT6 ( IER &= 0xffffffbf) but still I get interrupts on all the

data edges too. The IFR is being set and once I turn the interrupt back on,

the ISR is being called (not for different data but for the same data). Is there sometihng else that I am missing?

Please suggest.

Thanks,

Aditi.

Aditi,

What you are trying to do is not a straight-forward method. It will be tricky and may need some non-obvious logic methods used.

Turning off the IER bit keeps any interrupt signal transitions that set IFR from causing actual interrupts. If you have an IFR bit set and then enable it by setting its IER bit, then an interrupt will occur. You have to clear out any extraneous bits in IFR before setting a bit in IER. This should be done every time, even in main() before the first time you set IER in your program, but a lot of times people ignore that because they usually reach main() after a reset.

Regards,
RandyP

Hi Aditi,

Hope the discussion has helped you.

Best Regards,

Ankit

Hi,

I have tried and spent more than 2 weeks to get this to work. But found it is easy

implementing UART in the FPGA.

Thanks,

Aditi