Intrrupt Vector Table for C6746

Ujala,

Please refer to the TMS320C674x DSP CPU and Instruction Set Reference Guide . The section on Interrupts will help you understand what is in the IST and other important information.

Regards,
RandyP

Randy,

Thanks for your reply.

But I got an another query.

How are nested interrupts are handled in C6746.

As there is only one DMA interrupt for transfer completion (means for Tx and Rx same interupt will be used). So during the execution of Tx interrupt, if Rx interrupt comes, how will dsp handle this situation. I could not get it properly from Instruction Set Reference Guide.

It would be great if you guide me in this query.

Thanks in advance.

Regards,

Ujala

Ujala,

You will want to use TI-RTOS to handle your interrupts. It will allow you to set priorities for nesting of interrupts and enabling/disabling of interrupts.

For the EDMA3 module, the EDMA3 LLD (Low Level Drivers) includes a DMA interrupt dispatcher that handles multiple interrupts from the EDMA3 module.

Both are described on the TI Wiki Pages and in their respective documents.

Your Interrupt Service Routines should be designed to be very fast. You do not want to do any algorithms or big copies or such inside the ISR, but simply post a Semaphore or a SWI (SoftWare Interrupt) that will cause the real processing to be done shortly after the HardWare Interrupt (HWI) completes. This is explained in the TI-RTOS training on the Wiki. And this eliminates the worry about nesting vs. sequential handling of interrupts.

Regards,
RandyP

Dear Randy,

For now I want to know the address of ISPT so that I can initialize ISPB field of it with _intvectortable.

It was not mentioned in the main data sheet of c6746  and I also checked in Instruction Set Reference guide.

Kindly let me know about it.

Thanks..

Ujala,

In which document did you find these terms, ISPT and ISPB? I do not know them.

The two documents you mentioned, plus the Megamodule Reference Guide, should have the information you need. The Technical Reference Manual is a collection of documents that will also be worthwhile to search for a specific term in question.

Regards,
RandyP

Randy,

I am sorry for the mistake. Actually it is ISTP (Interrupt Service Table Pointer) mentioned in sprufe8b.pdf. It is supposed to be initialized with interrupt vector table.

But I did not find the address of ISTP.

Please guide me.

Ujala

Ujala,

There is no address for the Control Registers.

The existence and contents and assembly access method of the Control Registers are detailed in the CPU & Instruction Set Reference Guide.

The access method in C is discussed in the C Compiler User's Guide.

Regards,
RandyP

Dear Randy,

Thanks for your help. I am using CCS v5 and looking for how it works.

Regards,

Ujala Gupta

Ujala,

Since your questions are jumping around a bit, perhaps it would be good to look into one of our archived training classes available on TI.com and the Wiki. You can search either for training topics, like "C6713 training" (no quotes).

In CCSv5, open a Registers display window and select the control registers.

Regards,
RandyP