Hi TI experts:
we built our board based on C6748_LCDK with C6748 E chip on it. I started to do generic security boot. I used the tool from OMAPL138_C6748_Generic_Security-1.0.2-Setup.zip. First I used 'SecureHexAIS_OMAP-L138' to generate AIS file with .INI file as follows:
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; General settings that can be overwritten in the host code ; that calls the AISGen library. [General] ; Can be 8 or 16 - used in emifa busWidth=16
; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW BootMode=NAND
; 8,16,24 - used for SPI,I2C ;AddrWidth=8
; NO_CRC,SECTION_CRC,SINGLE_CRC crcCheckType=NO_CRC
; TRUE/ON or FALSE/OFF seqReadEn=ON
; Specify the symbol name for the boot finalize function ;FinalFxnSymbolName=none
; Security settings (keys, options, list of sections to encrypt, etc.) [Security]
; Security Type: GENERIC, CUSTOM, NONE securityType=GENERIC
; Boot Exit Type: NONSECURE, SECUREWITHSK, SECURENOSK ; NONSECURE = Device switches from secure type to non-secure type, jumping to loaded code ; (no secure kernel since no longer secure device). ; SECUREWITHSK = Device remains as secure type, secure kernel is loaded, allowing run-time ; security context switching. bootExitType = NONSECURE
; Option to include in the generated key header the flag to force the JTAG off ;genericJTAGForceOff=FALSE
; Encrypt section list (ALL or comma-separated list of section names) encryptSections=ALL
; CEK used for AES encryption of data - must be string of 32 hexadecimal characters encryptionKey=4A7E1F56AE545D487C452388A65B0C05
; Debug key ;keyEncryptionKey=0B94A91D33E597097F6C426F8F016872
; SHA Algorithm Selection genericSHASelection = SHA256
; Binary file containing secure key header for generic device ;genKeyHeaderFileName=key_hdr_sha256_enc.bin
;genKeyHeaderFileName=Specify binary file containing key header for generic devices. If this ; is not given, an unencrypted key header is generated from the ; genericSHASelection and the encryptionKey.
; This section allows setting the PLL0 system clock with a ; specified multiplier and divider as shown. The clock source ; can also be chosen for internal or external. ; |------24|------16|-------8|-------0| ; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| ; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| [PLL0CONFIG] PLL0CFG0 = 0x00190102 PLL0CFG1 = 0x00010306
; This section allows setting up the PLL1. Usually this will ; take place as part of the EMIF3a DDR setup. The format of ; the input args is as follows: ; |------24|------16|-------8|-------0| ; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| ; PLL1CFG1: | RSVD | PLLDIV3| ;[PLL1CONFIG] ;PLL1CFG0 = 0x00000000 ;PLL1CFG1 = 0x00000000
; This section lets us configure the peripheral interface ; of the current booting peripheral (I2C, SPI, or UART). ; Use with caution. The format of the PERIPHCLKCFG field ; is as follows: ; SPI: |------24|------16|-------8|-------0| ; | RSVD |PRESCALE| ; ; I2C: |------24|------16|-------8|-------0| ; | RSVD |PRESCALE| CLKL | CLKH | ; ; UART: |------24|------16|-------8|-------0| ; | RSVD | OSR | DLH | DLL | ;[PERIPHCLKCFG] ;PERIPHCLKCFG = 0x00000000
; This section allow setting the MPU1 or MPU2. If the ; rangenum is out of the allowed range then all the ranges ; (including the fixed range) take the start, end, and ; protection values. ; |------24|------16|----------8|----------0| ; MPUSELECT: | RSVD | mpuNum | rangeNum | ; STARTADDR: | startAddr | ; ENDADDR: | endAddr | ; MPPAVALUE: | mppaValue | ;[MPUCONFIG] ;MPUSELECT = 0x000001FF ;STARTADDR = 0x00000000 ;ENDADDR = 0xFFFFFFFF ;MPPAVALUE = 0xFFFFFFFF
; This section can be used to configure the PLL1 and the EMIF3a registers ; for starting the DDR2 interface. ; See PLL1CONFIG section for the format of the PLL1CFG fields. ; |------24|------16|-------8|-------0| ; PLL1CFG0: | PLL1CFG | ; PLL1CFG1: | PLL1CFG | ; DDRPHYC1R: | DDRPHYC1R | ; SDCR: | SDCR | ; SDTIMR: | SDTIMR | ; SDTIMR2: | SDTIMR2 | ; SDRCR: | SDRCR | ; CLK2XSRC: | CLK2XSRC | ; my change [EMIF3DDR] PLL1CFG0 = 0x19020102 PLL1CFG1 = 0x00000003 DDRPHYC1R = 0x000000C5 SDCR = 0x00134832 SDTIMR = 0x264A3209 SDTIMR2 = 0x3C14C722 SDRCR = 0x00000492 CLK2XSRC = 0x00000000
; This section allow setting the MPU1 or MPU2. If the ; rangenum is out of the allowed range then all the ranges ; (including the fixed range) take the start, end, and ; protection values. ; |------24|------16|----------8|----------0| ; MPUSELECT: | RSVD | mpuNum | rangeNum | ; STARTADDR: | startAddr | ; ENDADDR: | endAddr | ; MPPAVALUE: | mppaValue | ; ; This MPU control must happen after the DDR init or else the ; MPU control has no effect ;[MPUCONFIG] ;MPUSELECT = 0x000002FF ;STARTADDR = 0x00000000 ;ENDADDR = 0xFFFFFFFF ;MPPAVALUE = 0xFFFFFFFF
; This section can be used to configure the EMIFA to use ; CS0 as an SDRAM interface. The fields required to do this ; are given below. ; |------24|------16|-------8|-------0| ; SDBCR: | SDBCR | ; SDTIMR: | SDTIMR | ; SDRSRPDEXIT: | SDRSRPDEXIT | ; SDRCR: | SDRCR | ; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | ;[EMIF25SDRAM] ;SDBCR = 0x00004421 ;SDTIMR = 0x42215810 ;SDRSRPDEXIT = 0x00000009 ;SDRCR = 0x00000410 ;DIV4p5_CLK_ENABLE = 0x00000001
; This section can be used to configure the async chip selects ; of the EMIFA (CS2-CS5). The fields required to do this ; are given below. ; |------24|------16|-------8|-------0| ; A1CR: | A1CR | ; A2CR: | A2CR | ; A3CR: | A3CR | ; A4CR: | A4CR | ; NANDFCR: | NANDFCR | ;[EMIF25ASYNC] ;A1CR = 0x00000000 ;A2CR = 0x00000000 ;A3CR = 0x00000000 ;A4CR = 0x00000000 ;NANDFCR = 0x00000000
; This section should be used in place of PLL0CONFIG when ; the I2C, SPI, or UART modes are being used. This ensures that ; the system PLL and the peripheral's clocks are changed together. ; See PLL0CONFIG section for the format of the PLL0CFG fields. ; See PERIPHCLKCFG section for the format of the CLKCFG field. ; |------24|------16|-------8|-------0| ; PLL0CFG0: | PLL0CFG | ; PLL0CFG1: | PLL0CFG | ; PERIPHCLKCFG: | CLKCFG | ;[PLLANDCLOCKCONFIG] ;PLL0CFG0 = 0x00000000 ;PLL0CFG1 = 0x00000000 ;PERIPHCLKCFG = 0x00000000
; This section should be used to setup the power state of modules ; of the two PSCs. This section can be included multiple times to ; allow the configuration of any or all of the device modules. ; |------24|------16|-------8|-------0| ; LPSCCFG: | PSCNUM | MODULE | PD | STATE | ;[PSCCONFIG] ;LPSCCFG = 0x01030003
; This section allows setting of a single PINMUX register. ; This section can be included multiple times to allow setting ; as many PINMUX registers as needed. ; |------24|------16|-------8|-------0| ; REGNUM: | regNum | ; MASK: | mask | ; VALUE: | value | ;[PINMUX] ;REGNUM = 5 ;MASK = 0x00FF0000 ;VALUE = 0x00880000
; No Params required - simply include this section for the fast boot function to be called ;[FASTBOOT]
; This section allows configuration of one the systme IOPUs. ; The iopuNum field must be valid (0-5) and then mppaStart ; and mppaend fields allow setting a range of mppa MMRs to the ; same supplied mppa value. ; IOPUSELECT: | RSVD | iopuNum| mppaStart | mppaEnd | ; MPPAVALUE: | mppaValue | ;[IOPUCONFIG] ;IOPUSELECT = 0x000000FF ;MPPAVALUE = 0xFFFFFFFF
;[IOPUCONFIG] ;IOPUSELECT = 0x000100FF ;MPPAVALUE = 0xFFFFFFFF
;[IOPUCONFIG] ;IOPUSELECT = 0x000200FF ;MPPAVALUE = 0xFFFFFFFF
;[IOPUCONFIG] ;IOPUSELECT = 0x000300FF ;MPPAVALUE = 0xFFFFFFFF
;[IOPUCONFIG] ;IOPUSELECT = 0x000600FF ;MPPAVALUE = 0xFFFFFFFF
; This section allow setting the MPU1 or MPU2. If the ; rangenum is out of the allowed range then all the ranges ; (including the fixed range) take the start, end, and ; protection values. ; |------24|------16|----------8|----------0| ; MPUSELECT: | RSVD | mpuNum | rangeNum | ; STARTADDR: | startAddr | ; ENDADDR: | endAddr | ; MPPAVALUE: | mppaValue | ;[MPUCONFIG] ;MPUSELECT = 0x000001FF ;STARTADDR = 0x00000000 ;ENDADDR = 0x00000000 ;MPPAVALUE = 0xFFFFFFFF
; This function allows the user to selectively open up the ; the debug TAPs of the device. Since the function is not ; executed until the signature is checked, it does not ; pose a security issue. ; |------24|------16|----------8|----------0| ; TAPSCFG: | RSVD | tapscfg | [TAPSCONFIG] TAPSCFG = 0x0000FFFF
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I have USB-UART FT232RQ on the board as in C6748_LCDK, when I tried to use serial port to flashing as did for non-secures, it has the following issue:
(AIS parse): read magic word 0x41504954
(AIS Parse): Waiting for BOOTME... (power on)
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word Sync...
(AIS Parse): Performing Ping Opcode Sync...
(AIS Parse) : Processing command 0: 0x58535901
(AIS Parse): Performing Opcode Sync...
(Serial Port): Read error! (The operation has timed out)
(AIS Parse): I/O error in read.
Then I tried JTAG with NANDWriter supplied from TI, it has error in CCS5 as follows:
C674X_0: Error connecting to the target: Connect to PRSC failed
I tried both serial port and JTAG, both can not go through. Could you please help me what I should do and what I am missing?
Thanks!
Mike