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Cycle count doesn't equate to time elapsed

Hi,

I am trying to use the SYS/BIOS function Timestamp_get32() to profile some code. My test looks something like this:

Timestamp_getFreq (&freqInfo);

Int32 start = Timestamp_get32();

Task_sleep(15000);

Float deltaTime = 1000000.0f * (float)(Timestamp_get32() - start) / (float)freqInfo.lo; //freqInfo.lo = 300000000/372000000/456000000; set in cfg file

Firstly, I measured Task_sleep(15000); using a stopwatch and it seems to always run 1-1.5s over.. i.e. Task_sleep(15000); take 16-16.5 seconds.

Secondly, my deltaTime  value calculated is way off. This suggests to me that either the CPU clock is configured incorrectly, or this function is not counting cycles accurately. These are the values for deltaTime that were measured:

372 MHz 16.5s = 3.45s
300 MHz 16.5s = 0.683s
456 MHz 16.5s = 5.581s

I am running on a C6746. I am using the following PLL0 parameters in my gel file to configure the CPU clock. These were mainly taken from the C6748.gel file supplied with CCS v6.

Set_Core_456MHz() {
device_PLL0(0,18,0,0,1,3,9);
GEL_TextOut("\tPLL0 init done for Core:456MHz, EMIFA:114MHz\n","Output",1,1,1);
GEL_TextOut("\tIf your core voltage is not 1.3V then POWER OFF IMMEDIATELY!\n","Output",1,1,1);
}

Set_Core_372MHz() {
device_PLL0(0,30,1,0,1,18,5);
//device_PLL0(0,31,1,1,1,3,8);
GEL_TextOut("\tPLL0 init done for Core: 372MHz, EMIFA: 124MHz\n","Output",1,1,1);
}
Set_Core_300MHz() {
device_PLL0(0,24,1,0,1,11,5);
GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:25MHz\n","Output",1,1,1);
}

The function device_PLL0() configures the following parameters:

CLKMODE

PLLM

POSTDIV

PLLDIV1

PLLDIV2

PLLDIV3

PLLDIV7

I can see from the register view in CCS that

PLLDIV4 = 3

PLLDIV5 = 2

Should these dividers (4 and 5) be set considering they are not arguments to the function device_PLL0()?

Any idea what could be causing these incorrect cycle measurements?

Thanks

Brian

  • Brian,

    Wow. That is a big variation from reality in your time measurements, and an odd variation between the speed settings.

    My recommendation is to first confirm the clock speed you are running. Please see the Wiki article What is my DSP clock speed to get a program you can run that uses the DSP's TSC timestamp counter that is absolutely going to give you the number of clock cycles and the program offers a technique to validate your PLL settings.

    Then, using the examples from that program, use the TSC to check your delta time.

    SYS/BIOS uses a configuration setting to know what your clock speed is set to. If that is not the same as you actual clock speed, the system timer ticks will be off and that will affect the Task_sleep() results.

    We may have to move this to the TI-RTOS (new name for SYS/BIOS) forum for specific answers about the SYS/BIOS timestamp function. But we can see what the other results are first to figure out where to look next.

    Regards,
    RandyP

  • Hi Randy,

    Thanks for your suggestions, all very helpful. I ran your "What is my clock speed" program and this verified my PLL0 settings are correct.

    So, my issue is with Timestamp_get32(). 

    I tried your macro, TimerMacro(), and this was spot on, so I will just use this instead. 

    Many thanks

    Brian

  • Brian,

    Glad to hear. The TSC is what I always use since I have macros for it and know it will be accurate to the C674x core instruction cycles. It is easier in many cases than setting up BIOS and the timer functions, at least for my tests.

    Regards,
    RandyP