Hi,
I am trying to use the SYS/BIOS function Timestamp_get32() to profile some code. My test looks something like this:
Timestamp_getFreq (&freqInfo);
Int32 start = Timestamp_get32();
Task_sleep(15000);
Float deltaTime = 1000000.0f * (float)(Timestamp_get32() - start) / (float)freqInfo.lo; //freqInfo.lo = 300000000/372000000/456000000; set in cfg file
Firstly, I measured Task_sleep(15000); using a stopwatch and it seems to always run 1-1.5s over.. i.e. Task_sleep(15000); take 16-16.5 seconds.
Secondly, my deltaTime value calculated is way off. This suggests to me that either the CPU clock is configured incorrectly, or this function is not counting cycles accurately. These are the values for deltaTime that were measured:
372 MHz 16.5s = 3.45s
300 MHz 16.5s = 0.683s
456 MHz 16.5s = 5.581s
I am running on a C6746. I am using the following PLL0 parameters in my gel file to configure the CPU clock. These were mainly taken from the C6748.gel file supplied with CCS v6.
Set_Core_456MHz() {
device_PLL0(0,18,0,0,1,3,9);
GEL_TextOut("\tPLL0 init done for Core:456MHz, EMIFA:114MHz\n","Output",1,1,1);
GEL_TextOut("\tIf your core voltage is not 1.3V then POWER OFF IMMEDIATELY!\n","Output",1,1,1);
}
Set_Core_372MHz() {
device_PLL0(0,30,1,0,1,18,5);
//device_PLL0(0,31,1,1,1,3,8);
GEL_TextOut("\tPLL0 init done for Core: 372MHz, EMIFA: 124MHz\n","Output",1,1,1);
}
Set_Core_300MHz() {
device_PLL0(0,24,1,0,1,11,5);
GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:25MHz\n","Output",1,1,1);
}
The function device_PLL0() configures the following parameters:
CLKMODE
PLLM
POSTDIV
PLLDIV1
PLLDIV2
PLLDIV3
PLLDIV7
I can see from the register view in CCS that
PLLDIV4 = 3
PLLDIV5 = 2
Should these dividers (4 and 5) be set considering they are not arguments to the function device_PLL0()?
Any idea what could be causing these incorrect cycle measurements?
Thanks
Brian