How to change CPTS clock source via UBoot on DM8148?

Dave Beal

CPTS ref clock can be modified through the register RMII_REFCLK_SRC.

In U-boot it is configured in board_init function.

with regards

Mugunthan V N

I have the same problem as Dave Beal. Following http://processors.wiki.ti.com/index.php/TI81XX_PSP_Ethernet_Switch_User_Guide#Support_for_IEEE_802.1AS I'm using kernel built from ezsdk_dm814x-evm_5_03_01_15/board-support/linux-2.6.37-psp04.01.00.06.patch2 It is not clear to me how to determine what the other user of the clock is, so I can (maybe) disable that use. Otherwise, is it possible to reconfigure the clocks at linux kernel level, rather than by rebuilding u-boot? (aside: u-boot build appears to be broken with default make for this ezsdk) regards E Blennerhassett

(resending previous, hopefully with better formatting!)

I have the same problem as Dave Beal:

# ./ptpd2 -c -e -P
(ptpd notice) clock: 'cpts_rft_clk_ck' clock's parent 'audio_dpll_ck' is in use can't change the rate usecount = 2Using Linux PTP
Failed to set the rate -16
Hardware Clock API

Following http://processors.wiki.ti.com/index.php/TI81XX_PSP_Ethernet_Switch_User_Guide#Support_for_IEEE_802.1AS

I'm using kernel built from ezsdk_dm814x-evm_5_03_01_15/board-support/linux-2.6.37-psp04.01.00.06.patch2

How do I determine what the other user of the clock is, so I can (maybe) disable that use?

Otherwise,  how can I reconfigure the clocks while running linux (or at least in kernel driver), rather than by rebuilding u-boot?

(aside: u-boot build appears to be broken with default make for this ezsdk)

regards E Blennerhassett

Hi E Blennerhassett,

From the linux we don't have provision to change parent at run time. But we can change the parent from u-boot prompt.

Details can be found at

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_Clock_Framework_User_Guide

Same user guide talks about dumping all the clocks for understanding who is parent for what

Regards

AnilKumar

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Hi Anil

Can you explain why the AUDIO PLL was chosen as the CPTS clock source?.  There really should be a CPTS PLL that is not used by anything else. The AVB 802.1AS clock derived from the CPTS is independent of any audio or video clocks

Can you think of any reason of why we cannot use VIDEO0 or VIDEO1 PLL to clock the CPTS (assuming we are not using any video functionality of the DM8148)?.  I understand we have to set this up in u-boot.

thanks

Hi Stephan Turner,

Video PLL is used by video drivers, L3 PLL is used by lot of peripherals and more over McASP clock can be derived from other parts of clock circuitry. That is the reason why it is set to audio PLL. But most of the cases we are not using all together. So user have the flexibility to change CPTS clock parent depending on their requirement.

There is no reason for not using the Video - 0/1 PLL, if you are not using those PLL then you can use those PLL for configuring the CPTS.

Make sure that you are not using the PLL configured for the CPTS clock for other modules. Better look at the System clock diagram.

Regards

AnilKumar

Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!

Thanks Anil

We will use one of the Video PLLs for the CPTS and set it up in u-boot.

-steve