Can am335x starterware support rmii mode?

ge shuihuan

Intellectual 580 points

Other Parts Discussed in Thread: DP83848J

hello,

I'm using rmii interface connected to the phy dp83848j. And i have got the id of dp83848j(the value is 0x80017) .

After that , the Auto-Negotiation is Successful. Transfer Mode : 100 Mbps Full Duplex.

PHY link verified for Port 1.

But i can not ping the board from PC.

I'm using static IP .

lwipIfPort1.ipAddr = 192<<24 |168<<16 | 1<<8 | 200;
lwipIfPort1.netMask = 255<<24 |255<<16 | 255<<8 | 0;
lwipIfPort1.gwAddr = 192<<24 |168<<16 | 1<<8 | 1;

lwipIfPort1.ipMode = IPADDR_USE_STATIC;

Please help me . I'm trapped in this problem for very long time.

over 10 years ago

0 Ramesh Dandamudi over 10 years ago

TI__Intellectual 1480 points

Check the pinmux and MAC mode configurations for RMII interface.

Regards,

Ramesh D

0 ge shuihuan over 10 years ago

Intellectual 580 points

hello, Ramesh Dandamudi,

Thanks for reply.

my pinmux configuration is :

#define CPSW_MDIO_SEL_MODE 0x01

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE
| CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN
| CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL
| CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
| CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN
| CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL
| CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) =
CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN
| CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL
|CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) =
CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN
| CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL
| CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) =
CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN
| CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL
| CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =
CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE
| CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN
| CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL
| CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =
CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE
| CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN
| CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL
| CPSW_RGMII_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) =
CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE
| CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN
| CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL
| 0x0u;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
| CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN
| CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
| CPSW_MDIO_SEL_MODE;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN
| CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL
| CPSW_MDIO_SEL_MODE;

---------------------------------------------------------------------------------------------------

And my MAC mode :

void CPSWSlRGMIIEnable(unsigned int baseAddr)
{
HWREG(baseAddr + CPSW_SL_MACCONTROL) |= (CPSW_SL_MACCONTROL_GMII_EN
| CPSW_SL_MACCONTROL_IFCTL_A
| CPSW_SL_MACCONTROL_IFCTL_B);
}

void EVMPortRGMIIModeSelect(void)
{

UARTprintf("%s(%d): EVMPortRGMIIModeSelect: RMII 0xC5\n",__FILE__,__LINE__);
HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0xC5; // RMII1 clock sourced from pin, RMII2 clock sourced from CHIP PIN,
}

--------------------------------------------------------------------------

Is that any problem?

0 Ramesh Dandamudi over 10 years ago in reply to ge shuihuan

TI__Intellectual 1480 points

Check following configuration.

1. check CPSW_MDIO_SEL_MODE and CPSW_RGMII_SEL_MODE for pinmux on your board

3. CONTROL_GMII_SEL - Is RMII clock sourced from chip pin?

Regards,

Ramesh D

0 ge shuihuan over 10 years ago in reply to ge shuihuan

Intellectual 580 points

hi，Ramesh D，

I'm sorry for " #define CPSW_MDIO_SEL_MODE 0x01 " above, thats a mistake.

I'm using "#define CPSW_MDIO_SEL_MODE (0x00u)", and " #define CPSW_RGMII_SEL_MODE (0x01u) ".

Yes, RMII clock is sourced from chip pin, and i can test pad RXD_1, RXD_0 have 50MHz rate data infor.

0 ge shuihuan over 10 years ago in reply to ge shuihuan

Intellectual 580 points

And i check the link status with the function PhyLinkStatusGet(). It returns 1 standing for linking good. Is that right ?

0 Vladimir over 9 years ago in reply to ge shuihuan

Intellectual 850 points

I have the same problem. I see RMII signals, but do not see interrupt CPSW.

My physics KSZ8041 in RMII mode. I checked his connection schematics for technical documentation. I have connected via JTAG and checked trace the signal flow on lines TXD0, TXD1, TXEN, RXDO, RXD1, RXER, CRS to the processor. I run an example Startervare EnetLwip for EVMSK in dual MAC mode. First port work fine. Second port have a problem. Transmit packets are sent is good - I see them in Wireshark. Reception packages are not accepted. No interrupt CPSW hardware. RMII signals on lines when receiving packets visible is good. Packages are sent is good, hence clocking RMII to the side the processor correctly.

My pin MUX code is shown below:

/*Pin Mux for RMII2  */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) = 3;  //RMII2_TXD0
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) = 3;  //RMII2_TXD1
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = 3;  //RMII2_TXEN
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = 0x22; //RMII2_CRS
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) = 0x23; //RMII2_RXD0
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) = 0x23; //RMII2_RXD1
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) = 0x23;   //RMII2_RXERR
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = (1
        	| (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT)
        	| (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT));   //RMII2_REFCLK

dont know where to find cause of the problem. Any suggestions

0 Vladimir over 9 years ago

Intellectual 850 points

I have the problem. I see RMII signals, but do not see interrupt CPSW.

My pin MUX code is shown below:

/*Pin Mux for RMII2 */

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) = 3; //RMII2_TXD0

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) = 3; //RMII2_TXD1

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = 3; //RMII2_TXEN

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = 0x22; //RMII2_CRS

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) = 0x23; //RMII2_RXD0

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) = 0x23; //RMII2_RXD1

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) = 0x23; //RMII2_RXERR

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = (1

| (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT)

| (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT)); //RMII2_REFCLK

/*Pin Mux for RMII2  */

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) = 3;  //RMII2_TXD0

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) = 3;  //RMII2_TXD1

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = 3;  //RMII2_TXEN

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = 0x22; //RMII2_CRS

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) = 0x23; //RMII2_RXD0

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) = 0x23; //RMII2_RXD1

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) = 0x23;   //RMII2_RXERR

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = (1

            | (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT)

            | (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT));   //RMII2_REFCLK

dont know where to find cause of the problem. Any suggestions

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Can am335x starterware support rmii mode?