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How to configure AM335x DDR PHY Unknown Registers

Daisuke Maeda
Guru 20345 points

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/269394

The registers mentioned in above post can be found in the StarterWare v02.00.01.01.

\AM335X_StarterWare_02_00_01_01\bootloader\src\armv7a\am335x\bl_platform.c

Each of the following register is set to 0x0 in the initialization code.

 #define CMD0_SLAVE_FORCE_0                 (DDR_PHY_CTRL_REGS + 0x20)
 #define CMD0_SLAVE_DELAY_0                 (DDR_PHY_CTRL_REGS + 0x24)
 #define CMD1_SLAVE_FORCE_0                 (DDR_PHY_CTRL_REGS + 0x54)
 #define CMD1_SLAVE_DELAY_0                 (DDR_PHY_CTRL_REGS + 0x58)
 #define CMD2_SLAVE_FORCE_0                 (DDR_PHY_CTRL_REGS + 0x88)
 #define CMD2_SLAVE_DELAY_0                 (DDR_PHY_CTRL_REGS + 0x8C)

Should these registers configurations in the initialization code be removed or left?

Best regards,

Daisuke

  • 0
    TI__Guru** 116780 points
    Daisuke,

    It is recommended that you leave that register configuration in the initialization code. These registers probably come up with reset value 0 but for safe DDR configuration reasons it is better that the board library sets them to zero instead of relying on the reset values.

    I have checked the GEL files as well and they do have reference to these registers but don`t set them but our preference would be to set them to zero to ensure no software has accidentally chnaged that value before DDR initialization.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    Thank you for your reply.

    I have similar question for other registers right here: http://e2e.ti.com/support/embedded/starterware/f/790/p/397867/1964950#1964950

    I would like your answer if possible.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru** 116780 points
    DDR_PHY_CTRL_2 is similar to the DDR_PHY_CTRL_1. Only relevant configuration seems to be the last 4 bits in the register that configures the READ latency in terms of cycles. You can program the same value programmed in DDR_PHY_CTRL_1 into that register for normal operation.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    Thank you for your reply.

    I understand that  DDR_PHY_CTRL_2 register configuration in the initialization code can be left.

    CM_PER_L4FW_CLKCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_EMIF_FW_CLKCTRL registers are not applicable to GP devices. Can these registers configurations in the initialization code be left?

     \AM335X_StarterWare_02_00_01_01\bootloader\src\armv7a\am335x\bl_platform.c

    Best regards,

    Daisuke

  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    Daisuke Maeda said:
    CM_PER_L4FW_CLKCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_EMIF_FW_CLKCTRL registers are not applicable to GP devices. Can these registers configurations in the initialization code be left?

     \AM335X_StarterWare_02_00_01_01\bootloader\src\armv7a\am335x\bl_platform.c

    Can these registers configurations in the initialization code be left?

    I would like your answer if possible.

    Best regards,

    Daisuke

  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    I am sorry for asking the same question many times.

    CM_PER_L4FW_CLKCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_EMIF_FW_CLKCTRL registers can be found in attached AM335x TRM which is old revision (Rev. H).

     2337.AM335x_techincal_reference_manual.pdf

     \AM335X_StarterWare_02_00_01_01\include\hw\hw_cm_per.h

     \AM335X_StarterWare_02_00_01_01\bootloader\src\armv7a\am335x\bl_platform.c

    Each of CM_PER_L4FW_CLKCTRL and the CM_PER_L4FW_CLKSTCTRL registers is set to the reset value (0x2) in the initialization code. It should be allowed to leave these codes.

    CM_PER_EMIF_FW_CLKCTRL register is set to 0x2, not the reset value (0x0) in the initialization code. Is it allowed to leave this code?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru** 116780 points
    Sorry for the delayed response. We don`t see any issues leaving that initialization as part of the boot initialization code but to confirm we have pinged the design guys to provide their inputs on the configuration of these registers and we have not yet heard back from them.

    I will try to check with them again to see if I can get an confirmation.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    Thank you for your reply.

    Please tell me as soon as possible here if you get feedback from the design guys.

    Our customer cannot change their software for the their corporation rule until an confirmation is provided. They want to start change work in this week if possible.

    Best regards,

    Daisuke

  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    Can you tell me about the progress on this?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru** 116780 points

    The design teams response is that AM335x users shouldn’t have to touch those registers, that is why they were taken out of the TRM. They need to keep those regs in their default state that is observed after power on reset.

    If the code is configuring values different from the reset values,  we recommend that you take them out so their default values are untouched during initialization. 


    Regards,
    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 20345 points

    Hi Rahul-san,

    Thank you for your reply.

    I understand that the initialization code can be kept without a change because each of CM_PER_L4FW_CLKCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_EMIF_FW_CLKCTRL registers is set to their reset value (0x2) in the initialization code.

    For CM_PER_EMIF_FW_CLKCTRL register, the reset value is 0x0 in TRM Rev. H but the reset value is 0x2 when I check it by using emulator.

    Best regards,

    Daisuke