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Enable cache on L138 in SYS/BIOS, CCS5.1

Nikolaj Fogh
Prodigy 90 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

I am running SYS/BIOS 6.31.4.27 on a L138 C674x DSP and I am having some trouble enabling cache.

I use SYS/LINK to bootload the DSP from Linux, and are running some very simple benchmarks to try to figure out how much processing power I have. However, I can't seem to enable (or disable) the cache on the DSP. I am using the ti.sysbios.hal.Cache module, and calls to Cache_disable(Cache_Type_ALL) and Cache_enable(Cache_Type_ALL) does not make the program go faster or slower (I get around 10MFLOPS double precision).

I have made a custom RTSC platform where I have defined the DDR and 2 sections for the SYS/LINK shared memories (SR0 and SR1). I set the L1D and L1P cache to 32k and the L2 cache to 256k. All my code is set to run off the DDR.

I would have thought that it would be sufficient to call the Cache_enable() function to get it working, but apparently I'm missing something. I am quite new to CCS and RTSC, so there might be some fundamental things I am doing wrong.

Any ideas?

Best regards,

 - Nikolaj Fogh

  • 0
    Genius 4375 points

    Hi Nikolaj,

    From what you've posted, it seems that your RTSC platform is configured correctly.

    Could you use the ROV (RTSC object viewer) tool in CCS (Tools-> ROV) to view the state of L1D, L1P & L2 cache before and after you call Cache_enable/disable (check whether anything in the view changes)?  Open up the view for the ti.sysbios.family.c64p.Cache module.  If you don't see that L1 cache has been configured to 32K, L2 with 256K and that cache is enabled, then something might have gone wrong.

    Do you know whether your MAR registers are correctly configured?   If MAR bits are not enabled, then DDR will not be cached even if you've configured your platform to enable L1 & L2 cache.  You can use the ROV tool (ti.sysbios.family.c64p.Cache view) to check whether the MAR bits that correspond to the range of DDR that you want to cache are enabled.  Refer to the cdoc for the ti.sysbios.family.c64p.Cache module for more information about MAR registers and for code snippets.

    Regards,

    Shreyas

  • 0 in reply to Shreyas Oppanthaya
    Prodigy 90 points

    Hi

     

    I tried to look at the ROV. It says:

    address: 0xc3d21b3c

    L1PCacheSize: 32k

    L1PMode: Normal

    L1DCacheSize: 32k

    L1DMode: Normal

    L2CacheSize: 256k

    L2Mode: Normal

     

    The EnableMARs page the following is listed

    number 192-223 (Range 0xc0000000-0xdfffffff)

     

    So that all looks OK.

    However, looking at the L1DCFG, L1PCFG and the L2CFG registers, the bottom bits are all 0, so it seems that cache is not enabled anyway. Not even after the Cache_enable() call. I tried changing the values in the .cfg file by writing

    Cache.L1DCFG = 25428039;
    Cache.L1PCFG = 25428007;
    Cache.L2CFG = 25427975;

    However, I get errors saying that L1DCFG is sealed, so I guess I can only change those values through functions. I'm a bit puzzled as to how this works.

    I might just go configure the cache manually through the registers, but I would have like to have used the TI Cache library to do things the "right way".

     

    Best regards

      Nikolaj Fogh

  • 0 in reply to Nikolaj Fogh
    Prodigy 90 points

    Hi.

    I tried the following code:

            UInt32* L1DCFGp = (UInt32*)Cache_L1DCFG;
            UInt32* L1PCFGp = (UInt32*)Cache_L1PCFG;
            UInt32* L2CFGp = (UInt32*)Cache_L2CFG;
            *L1DCFGp = 0x7;
            *L1PCFGp = 0x7;
            *L2CFGp = 0x4;

    Which enables me to enable and disable the cache. Apparently, the cache was enabled as default. What I couldn't do was to disable the cache with a call to Cache_disable(). I would still like to figure out exactly why this is, but for now, I'm happy with configuring the cache this way.

    Best regards,

      Nikolaj Fogh

  • 0 in reply to Nikolaj Fogh
    TI__Mastermind 32475 points

    Nikolaj,

    I'm glad you seem to got things working but just a couple of clarifications:

    1.  If ROV says the Caches ared enabled and gives the size then they are enabled at the size.

    2.  I guess you figured out that Cache_L1DCFG, Cache_L1PCFG, and Cache_L2CFG are the Cache register addresses and not the Cache Settings.

    The 'cdoc' documentation found in your installation something like: C:\Program Files\Texas Instruments\bios_6_31_04_27\docs\cdoc\ti\sysbios\family\c64p

    Describes the API so please see the documentation for more information.  You can use Cache_setSize() to disable the Caches.

    Judah 

  • 0 in reply to judahvang
    Prodigy 90 points

    Hi.

    Whenever I change the cache registers manually using pointers, the ROV view changes, so it seems to read the values directly off the registers.

    The Cache_setSize() function works quite nicely. I can definately see the difference in performance when changing the cache sizes. It was something like that function I was looking for.

    However, Cache_disable(Cache_Type_ALL) still doesn't do anything which is a bit puzzling. I checked the documentation, and it says that it should disable the cache (except from L2?). How I see it, Cache_setSize() should set the sizes of the cache, but not touch whether it is enabled or disabled. You should then have to call Cache_enable() to actually enable the cache.

    Best regards

      Nikolaj Fogh