Data transfer between cores with MessageQ

onur akar

Prodigy 100 points

Other Parts Discussed in Thread: SYSBIOS

Hi,

platform evm 6678,
IPC 1.22.05.27
sys/bios 6.31.04.27
ccs 5.01

C6678 device functional simulator, little endian

I am creating a messageQ for interprocessor communication among the two cores [CORE0, CORE1] of my evm6678 board.

I tried to use the MessageQ example program message_multicore.c (ipc directory/packages/ti/sdo/ipc/examples/multicore/c6678).

I made small modifications on the program in order to send an array of integers from Core0 to Core1. Therefore I edit the content of the message as shown below:

Typedef struct TstMsg

{

MessageQ_MsgHeader header;

int16_t *dataPtr;

}TstMsg;

TstMsg *msg;

Even though it seems like Core1 can get the message from Core0, array values that was attached to the message is not seemed to be modified. I fill the array with the int values. But Core1 still sees that array with zero values filled instead.

My suspicions about possibble problem :

1. cache_wb or cache_inv should be performed. Can i use this only by adding #include <ti/sysbios/hal/Cache to the program, or does there need to be something done on .cfg file of the project?

2. I have used "Generated Linker Command File". I think this is a default linker file generated by the compiler, do I need to make changes on that? I tried that but I could not locate the .cmd file for my project. Which memory should I put the Data, Code section on (L2SRAM, MSMCSRAM) for data sharing between cores?

3. Lastly, on one of the postings, I read that arbitration may be needed. I have no idea why and how can be used for my project.

What changes do i need to do on the messageq example in order to be able to send data from one core to another?

Is the MessageQ most appropriate method for data sharing between cores ?

Thanks.

over 14 years ago

0 judahvang over 14 years ago

TI__Mastermind 32475 points

Answers to your questions:

1. If the arrays are coming from a cacheable memory region (shared L2 memory and DDR are cacheable by default), then you need to do a Cache_wb() or Cache_wbInv() of the data after you modify it before sending it to the remote processor. You can only use these APIs by including the header file as you specified.

2. If you are using SYSBIOS, a linker command file is generated for you and included in a CCS project already. There should be no need of adding your own linker command file unless you have some sections of your own that need to be placed. Changes should not be made in the generated linker command file because those changes will get overwritten when the linker command file gets regenerated. Did you read the getting started guide for BIOS and the users guide for IPC yet? Or did you try out the examples that come with BIOS and IPC?

3. Arbitration is needed because you don't want two cores to be over riding one another's data especially if you plan on building a single executable and loading from all cores.

You don't need to make any changes to messageq example to be able to send data from one core to another. This example should do that by default because its purpose is to show you how to send data between cores. Yes, MessageQ is most appropriate method for sharing data between cores. If using MessageQ, there's no need to do Cache_wb or Cache_wbInv since it does it for you.

Judah

0 onur akar over 14 years ago in reply to judahvang

Prodigy 100 points

Hello Judah,

Thanks for the answers, I am using SYSBIOS and working on MessageQ example that is included in IPC. I have read almost all of the technical manuals, and guides.

I will have one more question:

I would like to generate an array and put it into DDR memory (because the array size is large) and then transfer this array to other cores to make some further processin on it. I think i need to add a section for this array on linker command file. Somehow I can not find the generated linker command file for my project.

Can you guide me finding the generated linker command file ?

Onur

0 judahvang over 14 years ago in reply to onur akar

TI__Mastermind 32475 points

Onur,

Make sure you data align the array structure to 128 bytes (This is the cache line size of L2).

Are you using CCS for your project? If you are you should find a file called "linker.cmd" under the Debug/configPkg of your project. If you don't find that file then search for a file with the extension *.xdl. You actually don't want to modify this file though since its generated. Using CCS v4 or v5, it should allow you to add your own linker command file to the project and both will be recognized.

If not using CCS, I think you can add a linker command file using the linker options (-l <Name Of Your Linker.cmd>).

Judah

0 onur akar over 14 years ago in reply to judahvang

Prodigy 100 points

Hello Judah,

1. In my application I am using one of the dsplib routines called DSP_fft16x16(w_16x16, N, x_16x16, y_16x16); That routine requires the data to be 8 bytes alignment.

Therefore i included to my code:

#pragma DATA_ALIGN(x_16x16, 8);

Is it possible to apply 128 bytes data alignment again to this data in the same code?

2. I am using CCS V5. I could find the linker.cmd file. When I open the file, inside it is written :

"C:/Documents and Settings/onur akar/workspace/MCORE/Release/configPkg/package/cfg/message_multicore.pe66.obj"

"C:/Documents and Settings/onur akar/workspace/MCORE/Release/configPkg/package/cfg/message_multicore_pe66_x.xdl"

I also found these two files, Thanks...

Thanks for all

Onur

0 judahvang over 14 years ago in reply to onur akar

TI__Mastermind 32475 points

Onur,

You should replace #pragma DATA_ALIGN(x_16x16, 8) with #pragma DATA_ALIGN(x_16x16, 128);

You need the 128 bytes for the cache alignment. 128 bytes means that it will also be 8 bytes aligned.

So in your case, things look a bit different than mine but nevertheless, the .xdl file is the generated file.

Is the linker.cmd file being generated in your case? If not, you could probably add your stuff directly to linker.cmd. I know the *.xdl file is being generated for sure.

Judah

0 onur akar over 14 years ago in reply to judahvang

Prodigy 100 points

Judah,

Yes, linker.cmd is generated in my project, and when i look into it, i see those lines written on it.

"C:/Documents and Settings/onur akar/workspace/MCORE/Release/configPkg/package/cfg/message_multicore.pe66.obj"

"C:/Documents and Settings/onur akar/workspace/MCORE/Release/configPkg/package/cfg/message_multicore_pe66_x.xdl"

some part of the .xdl file is as below :

MEMORY

{

L2SRAM (RWX) : org = 0x800000, len = 0x80000

MSMCSRAM (RWX) : org = 0xc000000, len = 0x400000

DDR3 : org = 0x80000000, len = 0x20000000

}

Onur

0 onur akar over 14 years ago in reply to onur akar

Prodigy 100 points

Hello Judah,

I could generate my linker.cmd file and add it to the project. Now the block size data can be put in the DDR3 memory.

Thanks for your great help.

Onur

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Data transfer between cores with MessageQ