• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 1175 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SYSLINK and OMAPL138: using internal shared memory for SYSLINK shared regions

claudio potenza
Intellectual 400 points
Other Parts Discussed in Thread: OMAPL138

Hi all,

I am using SYSLINK on a OMAPL138 device to have the DSP and ARM (running Linux) to communicate to each other.

I have TI_CGT_C6000_7.4.2;  bios_6_35_01_29;  ipc_1_25_02_12;  syslink_2_21_01_05;  xdctools_3_24_07_73

At the moment I am playing with the messageQ example (ex02_messageq) which exchanges a few messages. This examples creates two shared regions for SYSLINK use ("SR0" and "SR1").

I can now run this example without problems when the shared regions are in the main DDR. I can modify shared/config.bld at will to move the shared regions and the DSP code & data area around.

What I am NOT able to do is to move the two regions in the OMAPL138 128kbytes internal device memory.

I tried to simply modify the address of the two regions in shared/config.bld so that they end up in the shared region. But this doesn't work as that area is already defined inside the platform (I am using the ti.platforms.evmOMAPL138 platform) as L3_CBA_RAM and so there is a conflict.

I have also tried to generate my own platform without that L3_CBA_RAM area but so far I've not been able to make this work either.

Can anyone shed light on what is the shortest route to achieve my goal?

thanks

  • 0
    Intellectual 400 points

    Has anyone any hints/suggestions on how to setup things so that I can use the OMAPL138 internal shared memory for SYSLINK shared regions?

  • 0 in reply to claudio potenza
    TI__Expert 6860 points

    The SysLink examples use DDR for SharedRegions as it's memory that needs accessible by both cores (ARM9 & C674X).  The platform that is uses (ti.platforms.evmOMAPL138) already has predefined internal memory sections:

    IROM                  11700000   00100000

    IRAM                  11800000   00038000

    L3_CBA_RAM  80000000   00020000

    To configure/place SharedRegion0 into L3_CBA_RAM, set the following in your application's configuration file (Dsp.cfg):

    SharedRegion.setEntryMeta(0,
        new SharedRegion.Entry({
            name:           "SR0",
            base:           0x80000000,
            len:              0x00020000,
            ownerProcId:    MultiProc.getIdMeta("HOST"),
            cacheEnable:    false,
            isValid:        true
        })
    );

    This will create an SR0 with spanning the entire L3 region.  This assume nothing else is being placed in this regions.

  • 0 in reply to Arnie Reynoso
    Intellectual 400 points

    Arnie,

    thanks.

    I originally tried to set the address for "SR_0" inside config.bld, not Dsp.cfg and I was getting an error at link time to the effect that SR_0 was overlapping with L3_CBA_RAM.

    Now it is building correctly.

    I'll let you know if it is also working correctly (I think that the L3 region is not used by ARM nor DSP at the moment).

  • 0 in reply to claudio potenza
    TI__Expert 6860 points

    The config.bld defines an external Memory Section called SR_0, which the DSP application happens to create/config SR0 into via the cfg file.  What really defines where SharedRegions are created and placed is in the *.cfg file itself.