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C6678 IPC Notify : what happens behind the scenes

Clement FR
Genius 4750 points
Other Parts Discussed in Thread: SYSBIOS

Hello everyone,

I have a few questions about the implementation of IPC Notify on C6678 :

a) Does the c6678 have several interrupt lines (line id parameter) or only one ? I haven't seen evidence of more than 1 but I want to be sure.

b) From the sources below, here's my understanding :
Notify events (purely software, not related to any particular mapping) are multiplexed on a single interrupt event which ID is 91 on C6678. This interrupt event is mapped to the interrupt vector 5 (it is modifiable). Tell me if I'm wrong.

c) Does it mean that I can't use interrupt vector 5 for other interrupts (non IPC related) ?

d) When Core 0 does a NotifySendEvent to Core 3 : does it write a 1 in the IPCG field of IPCGR3 ? From what I saw it only wrote 0x80 on IPCGR0 (confusing me)

e) and when Core 3 sends a NotifyEvent to core 0, what does it do regarding IPCGRx registers ?

f) is it possible to see IPCGRx registers in the register view of CCS ? (Haven't found it, I use the memory browser instead)

Thank you,

Clément

(sources)

http://e2e.ti.com/support/embedded/bios/f/355/p/231655/814025.aspx#814025
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/210716.aspx
http://e2e.ti.com/support/embedded/bios/f/355/t/139063.aspx
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/165208/853925.aspx#853925
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/260601.aspx


  • 0
    TI__Intellectual 2745 points

    Hello again!

    These are some great questions and thank you for doing your research beforehand.  Let me see what I can figure out on my end and I'll get back to you.

    Sincerely,

    John Demery

  • 0 in reply to John Demery
    Genius 4750 points

    Hi John,

    Looking forward seeing your answers. Thanks

    Clément

  • 0
    TI__Expert 6860 points

    Clement Mesnier said:
    Does the c6678 have several interrupt lines (line id parameter) or only one ? I haven't seen evidence of more than 1 but I want to be sure.

    I also only see one but maybe some HW folks looking at this can correct me if I'm wrong.

    Clement Mesnier said:
    b) From the sources below, here's my understanding :
    Notify events (purely software, not related to any particular mapping) are multiplexed on a single interrupt event which ID is 91 on C6678. This interrupt event is mapped to the interrupt vector 5 (it is modifiable). Tell me if I'm wrong.

    That's correct.

    Clement Mesnier said:
    c) Does it mean that I can't use interrupt vector 5 for other interrupts (non IPC related) ?

    It not recommended but if your system requires interrupt vector 5, you can configure the SysBios IPC software stack to change this (as you've seen in your other referenced links)

    Clement Mesnier said:

    d) When Core 0 does a NotifySendEvent to Core 3 : does it write a 1 in the IPCG field of IPCGR3 ? From what I saw it only wrote 0x80 on IPCGR0 (confusing me)

    e) and when Core 3 sends a NotifyEvent to core 0, what does it do regarding IPCGRx registers ?

    We're looking into this and will be getting back.

    Clement Mesnier said:
    f) is it possible to see IPCGRx registers in the register view of CCS ? (Haven't found it, I use the memory browser instead)

    I've been unable to view these registers as well.  Maybe someone of the HW team or CCS team can chime-in.  You may have better luck post this specific question there.

  • 0
    TI__Expert 6860 points

    To follow up with your questions below:

    Clement Mesnier said:

    d) When Core 0 does a NotifySendEvent to Core 3 : does it write a 1 in the IPCG field of IPCGR3 ? From what I saw it only wrote 0x80 on IPCGR0 (confusing me)

    e) and when Core 3 sends a NotifyEvent to core 0, what does it do regarding IPCGRx registers ?

     Bit 0 is set to generate interrupt.  Bits 4-7 is set to specify the interrupt generation source. The convention is that bit 4 (SRCS0) is used for core 0, bit 5 (SRCS1) for core 1, etc... .

  • 0 in reply to Arnie Reynoso
    TI__Genius 12065 points

    1. I think there is only one IPC event connected to CorePac INTC in C6678 as "IPC_LOCAL" (event #91).

    2. The IPCGRx registers are chip level registers, and are not shown in CCS CPU register view. So it is better to observe them in memory browser just as observing the other peripheral registers.

  • 0 in reply to Steven Ji
    Genius 4750 points

    Everyone,

    Thank you for your answers. My questions a) b) c) f) are answered.

    Concerning
    d) When Core 0 does a NotifySendEvent to Core 3 : does it write a 1 in the IPCG field of IPCGR3 ? From what I saw it only wrote 0x80 on IPCGR0 (confusing me)
    e) and when Core 3 sends a NotifyEvent to core 0, what does it do regarding IPCGRx registers ?

    In the data manual
    IPCGR0 is 32-bit wide at @0x02620240
    IPCGR3 @0x0262024C

    Core 0 sends Notify_sendEvent( 3, INTERRUPT_LINE, EVENTID, 0, TRUE); (to core3)
    in the memory browser I should see  0x11 (0b10001) @IPCGR3

    Core 3 sends Notify_sendEvent( 0, INTERRUPT_LINE, EVENTID, 0, TRUE); (to core0)
    in the memory browser I should see  0x81 (0b10000001) @IPCGR0

    I'll try this later (could be days) and let you know if I got what I expected.

    Regards,
    Clément

  • 0 in reply to Clement FR
    TI__Mastermind 32475 points

    Clement,

    Answer to D.  Yes, it writes a 1 in IPCGR3...more correctly as you listed above, it writes 0x11 to IPCGR3.

    Answer to E.  It writes 0x81 to IPCGR0.

    I'm not sure what you will see in the memory broswer at the IPCGRx addresses.  If you halt all cores and just run the 1 core then you might see what you are expecting.

    Judah