DS320PR1601RSCEVM: DS320PR1601RSCEVM

Hi Shekha,

Thank you for reaching out regarding these questions.

If a 4x4 MCIO connector is desired for your design, side-band signals such as PRSNTx# and PERST# can be routed to the PDx-x pins of the DS320PR1601 when combined with logic. The DS320PR1601 data sheet, Table 8-1 and Figure 9-2, highlight the use of PRSNTx# and PERST# sideband signals. Please refer to the following layout document for practice of terminating un-used PCIe side-band signals: https://www.ti.com/lit/an/snla426/snla426.pdf?ts=1697653251384 

The DS320PR1601 does not require a PCIe REFCLK, therefore no clock buffer is required for the device.

Best,
David

Hi Shekha,

This redriver can support 8 x2 link width, as it acts as an analog boost stage to the PCIe link. However, if hot plug support is needed for x2 links, PD of specific channels will need to be accounted for at the firmware or software level, as the DS320PR1601 includes only 4 power-down (PD) pins.

EEPROM is not required for the DS320PR1601, as the device can alternatively be programmed using SMBus / I2C.

A clock buffer would be needed to fan out the global REFCLK to 4 MCIO ports.

Best,
David

HI Shekha,

I've just granted you access to the secure resources folder containing this document. Please be on the look out for an email with instructions on how to access this folder.

Best,
David

Hi Shekha,

Regarding the posed questions:

1. The mapping of DS320PR1601 channels would be the same for this configuration. However, it should be considered that each x4 bifurcated port may have its own lane numbering if the link is bifurcated (for example, each x4 port could be numbered lanes 0-3, but the physical connections to the DS320PR1601 device would remain unchanged).
2. The addresses of the DS320PR1601 are set via pin-strap, outlined in Table 1-1. Each DS320PR1601 comprises of 8 SMBus/I2C addresses which correspond to various channel banks of the device, also outlined in Table 1-1 and Table 1-2. For example, if it is desired to read ID1 from the SMBus address 0x18, register address 0xF1 would need to be specified.
3. I believe there is a slight nomenclature difference between these two documents. Table 8-1 of the data sheet may help to clear confusion regarding the address pins and their channel mapping.

Best,
David

Hi Shekha,

Please allow me to summarize your questions and my answers below the quoted questions:

SHEKHA SHOUKATH said:

Also in DS320PR1601 EVM user manual it is specified that all PD  pins for all channels has to be GND to enable all channels and for x16 lane application. Will it differ if the output side is 4x4 ports?

How this pin is manually triggered?

is the respective I2C register is PD override register or Rx detect control register?

could you please tell how the above two registers has to be used?

The RX Detection state machine's functionality and timing is controlled by both the PDx pins and the SMBus/I2C registers, if desired. As stated in Table 8-1, when PDx pins are driven low, the PCIe RX Detect state machine is triggered. The PCIe RX Detect state machine can also be manually triggered through the SMBus/I2C channel register specified by [Channel Register Base Address + Offset = 0x04]. Separately, the PD override register located at [Channel Register Base Address + Offset = 0x05] can be used to manually override the Power Down (PD) control of each device channel. These two registers are defined in the DS320PR1601 data sheet.

SHEKHA SHOUKATH said:

Are the registers General register,Device ID0 register, Device ID1 register, common for all channels?

The four registers listed above are not common for all channels. These four registers are common for each Bank of registers, which are each located at a separate SMBus/I2C address. Each bank is associated with four channels, but each channel does not contain all share registers associated with the bank.

SHEKHA SHOUKATH said:

In the programming guide  table 2-4, channel register base address is specified, but there up to channel 7 is specified. How can we access other channels upto 15.

Also by broadcast write channel bank 0 and 1(0x80), will 16 channels on A and B side be written?

Channels 8-15 may be accessed through the same methodology, though I agree that it is not inherently clear in the document. Table 1-2 and Table 1-3 in the programming guide outline the mapping of channel banks, I2C addresses, and channels (channel banks). Please see the following example below as supplement to Tables 1-2 and 1-3.

SHEKHA SHOUKATH said:

How to decide the CTLE index value?

In programming guide, table 4-1, flat gain of 0dB is specified for multiple CTLE index values(0,1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18).It is mentioned in the EVM user manual and DS320PR1601 datasheet flat gain of 0dB is better and the default value.

The CTLE index value is associated with a high-frequency boost and linear equalization given in data sheet section 7.3.1. The chosen CTLE value is dependent on your system configuration (placement of the DS320PR1601, insertion loss of the system, etc.).
The listed flat gain values in the device programming guide Table 4-1 are listed as programming examples for the EQ Control Register (Channel register base + offset = 0x01) and EQ Gain / Flat Gain control register (channel register base + offset = 0x03).

SHEKHA SHOUKATH said:

As you mentioned "for hot plug support for x2 links, PD of specific channels will need to be accounted for at the firmware or software level, as the DS320PR1601 includes only 4 power-down (PD) pins".    Could you please provide some more clarification in the said case.

Please see my response to the first quoted question from you for some clarity on this question. For a x2 bifurcation configuration, individual channel registers for PD and RX Detect for the channels connected to each x2 port should be manually controlled or programmed when considering hot plug support.

Best,
David

Hi Shekha,

Thank you for providing the pinout diagram. I believe your assumption is correct, but you should double-check with the intended endpoints used with this MCIO connector and their needed sideband signals. I am unsure if each x2 port would require these signals.

PRSNTx# signals are used for add-in card detection. Please find the definition of PRSNTx# in the PCI Express CEM specification.

Regarding bifurcation, I believe TX/RX 0-3 would be split into 0-1, 2-3, and so forth for each other x4 port. I am unsure if there is a standard for this split.

Additionally, if you would like to ask a different question from the intended questions of the original thread, please create new E2E thread .

Best,
David

Hi Shekha,

I believe this is a slight nomenclature difference. For example, Pins A16 and A17 of connector P1 (gold finger/edge connector) on the DS320PR1601 EVM are labeled as nets PER0_P/N and are connected to DS320PR1601 pins P10 and M7, which are B_PETn/p0. Thus, the transmitter output from the redriver device would then connect to the receive input of the gold finger connector - TX0P/N - to be transmitted to the receiver of the root complex.

Best,
David