AM6442: PRU-ICSSG core

Hi,

Are you working with Linux or RTOS for your use case?

Also, is there a specific reason why you want to use the main domain GPIO pins instead of a PRU GPIO? Some more information of your use case would be helpful.

Regards,

Nitika

I am working with Linux. For our AM6442 based custom board, we supposed to use GPIO1_56 as an interrupt-enabled GPIO for PRU. The interrupts are expected in msec range. Other gpi/gpos are already used for other peripherals.  How to configure the GPIO1_56 for PRU.

Hi,

Thank you for the information.

I have directed your query to our Linux expert. Please allow them some time to get back to you.

Regards,

Nitika

Hi Nitika,

I just wanted to kindly follow up on my previous inquiry regarding the configuration of GPIO1_56 as an interrupt-enabled GPIO for PRU on our AM6442 custom board. I understand this is being directed to the Linux expert, and I appreciate your support. Could you please provide an update on when I might expect a response?

Thank you again for your assistance!

Best regards,
Shiny K George

Hello,

If you only need millisecond precision, then an external GPIO module instead of the PRU's internal PRU GPI / PRU / GPO signals should be fine from a design standpoint.

Is that GPIO1 being used by any other part of your system, or is it dedicated for the PRU's use?

Regards,

Nick

Hello Nick,

Thank you for your response.

On our board, GPIO0_x is allocated for Linux, while GPIO1_x is divided between the real-time cores and PRU. I need to configure GPIO1_56 as an interrupt input to the PRU. Could you advise on the best approach to access and utilize this pin within this setup?

Thank you for your assistance.

Hello,

I am reassigning your thread to a member of our MCU+ team to discuss configuring GPIO interrupts from one GPIO instance to go to multiple MCU+ / bare metal cores.

Please note that this team member may be on vacation this week for holidays in India. If you do not get a response this week, please ping the thread during the week of November 4.

Regards,

Nick

Hello Nick,

Thank you for the update and for reassigning the thread to  member of the MCU+ team. I appreciate the heads-up regarding the potential delay due to holidays. I’ll follow up on this thread if I don’t hear back by the week of November 4.

Regards,

Shiny K George

Hi Shiny,

You can configure the GPIO1_x to interrupt PRU core as the GPIOMUX Interrupt Router has dedicated connection to PRU cores.

Please refer below image.

Are you facing any difficulty in configuring the above pins to generate interrupt at PRU cores? Can you please share the code with us?

Regards,

Tushar

Hi Tushar,

Thank you for your support. Could you guide me on configuring resources for this task? I’m interested in understanding the best approach and any recommended practices for effective resource configuration.

Regards

Shiny K George

Hi Shiny,

You will need to update the rm-cfg.yaml file with the proper resource allocation for GPIOMUX router to PRU cores.

To know more about interrupt management, please refer interrupt_cfg.

You can use the resource partitioning tool to do resource allocation. Please refer faq-how-to-use-k3-resource-partitioning-tool-with-processor-sdk-v9-0-or-v9-1.

Please take reference from the existing GPIO input interrupt example that routes interrupt to R5F cores. Similarly you can make changes to route interrupts to PRU cores.

Regards,

Tushar