DP83867CR: PHY will die after 6+, 10+ hours running

Hi Chris,

Kindly confirm the following for further debug :

1. Board #1 and board #2 are same boards (same schematics, layout and components).

2. Both of these boards worked fine after power up and only after some hours the packet transfer stops.

3. Can you make a block diagram of test setup? Is packet transfer ok/not ok the test?

4. Is there a difference in the input clock source (crystal/external clock) of the phy used in 100M and phy used in 1G mode?

5. For board #2, can you measure frequency difference between clkout 25MHz of phy and gtxclk 25MHZ of MAC?

6. For board #2, are rx_d0, rx_d1,rx_d2 and rx_d3 lines also toggling?

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Regards,

Vikram

Hi Vikram,

Thanks for your response.

For 1/, yes, they are two boards in the same batch.

For 2/, yes, some boards can even work for 16 hours or 20 hours.

For 3. all the packets are transferred well at the very beginning, I draw a diagram below.

For 4/, no difference, both boards source external oscillator.

For 5/, what kind of difference do you want to me to measure, is there a fixed phase difference between these two clcok, I can only measure with oscilloscope.

For 6./, I can make measurement and update tomorrow.

There are two DP83867 and a switch connected with the same MDC/MDIO bus,

- DP83867-1 is connected with public Gigabit network, and and it would be down after 6 hours or 10 hours.

- DP83867-2 is connected with 100M network, at least I didn't find it down during days of testing.

- The switch is also working well.

Today I wrote some scripts inside linux of AM3352, so it will keep reading registers of DP83867-1, I'm using register 0x0003, it must be 0xA231 per datasheet page59, while in 10000 times reading, I found there would be about 30 times with value like 0x0110, or others, I'm one hundred percent of sure that the MDC/MDIO bus is pretty clean, no signal integrity problem, MDC is 1MHz, and MDIO will change in the falling edge of MDC.

So my question is, given a device under MDC/MDIO bus, should I read 0xA231 all the times? Is it driver related issue?

Thanks

Chris

Hi Chris,

For 5 : Lets measure the frequency difference between the clocks that is how much is the ppm differnece between them?

For 6 : What is your observation?

Regarding MDC/MDIO : Yes it should read correct value every time. What is the phy address of 867-1? Can you share the straps connected to pins to make this phy address possible? Also is MDC clock running continuously or does it stop after every read?

Also do you think that there can be glitches in 25MHz reference clock to the phy (turning on and off) because of some system level loop? May be you can look at the external oscillator's schematic and see if there is any signal which can potentially turn-off the clock to phy.

Also when this problem of phy ID or data loss occurs, does toggling resetn or writting register 0x001F=8000 recovers the issue?

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Regards,

Vikram