LMH0340: LMH0340 Timing Diagram and Serialization Factor

Anil Sutej Malayanur

Prodigy 60 points

Part Number: LMH0340

Hi,

We have requested for the code but haven't received any update or mail from TI.

We just need to know the timing diagram and we can work on the code.

If our understanding is correct

1. we have to send 5 LSB's @ Posedge and next 5 MSB's @ Negedge

2. What is clock rate ? 148.5 MHz ?

Please suggest is our understanding is correct or share the code

Thanks

Anil Sutej

over 4 years ago

+1 Nasser Mohammadi over 4 years ago

TI__Guru* 93670 points

Hi Anil,

1). With respect to the FPGA IP, please send me a friend request with your company email address. I can follow up so you can get access to the FPGA example IP.

2). Your understanding is correct. 5-bits per edge, is like having 10-bits per clock cycle. 10 bits multiply by the TXCLK is the actual SDI line rate.

Regards,,Nasser

0 Anil Sutej Malayanur over 4 years ago in reply to Nasser Mohammadi

Prodigy 60 points

Dear Nasser,

0 Anil Sutej Malayanur over 4 years ago in reply to Nasser Mohammadi

Prodigy 60 points

Dear Naseer,

Thanks for the the prompt response.

I will do as suggested

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LMH0340: LMH0340 Timing Diagram and Serialization Factor