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DS90UH941AS-Q1: Internal CLK/External CLK/DSI CLK setting

Roy Chou1
Genius 14545 points
Part Number: DS90UH941AS-Q1
Other Parts Discussed in Thread: LMK61E0M

Hi Team,

We used internal CLK to achieve internal Patgen. (following the https://www.ti.com/lit/an/snla132g/snla132g.pdf?ts=1624449102212&ref_url=https%253A%252F%252Fwww.google.com%252F)

And our MODE_SEL-CLOCK MODE set '0' then.

And we change to use external clk to achieve internal patgen. We connect the osc on REF0. Should we modify other register?

And next step will use DSI CLK, we will change  MODE_SEL-CLOCK MODE to '1' . Should we modify other register?

Roy

  • 0
    TI__Guru** 103215 points

    Hello Roy,

    For PCLK from external REFCLK, you would need to set 0x56[1:0] = b'01, and then in the PATGEN config, configure external PCLK mode by setting 0x65[3] = 1. For using PCLK from DSI clock, then 0x56[1:0] = b'00 (this is the default value), and 0x65[3] = 1.

    Please also make sure to set 0x4F[7] = 1 if the DSI source is in continuous clock mode (regardless of whether you are using PCLK from DSI clock or external REFCLK mode in 0x56). 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Genius 14545 points

    Hi Casey,

    Thanks for detailed information. And I would like to check with you about REFCLK spec. In EVM, I saw that we used LMK61E0M as external CLK and its VDD = 3.3V which means that clk amplitude = 3.3V.

    And I saw the datasheet saying that REFCLK(max) should VDDIO+0.3V. And EVM VDDIO = 1.8V. I think there is conflict between spec and EVM connection.

    May you let me know if this is an issue in the condition?

    In short, could we use amplitude = 3.3V REFCLK as external clk when  VDDIO = 1.8V.

    Regards,

    Roy

  • 0 in reply to Roy Chou1
    TI__Guru** 103215 points

    Hello Roy,

    Yes, the 941AS can accept 3.3V on the REFCLK when using either 3.3V VDDIO or 1.8V VDDIO - it will not damage the device

    Best Regards,

    Casey