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DS125DF410: After configuring DS125DF410 device fail to lock

Daniel Ram
Prodigy 20 points
Part Number: DS125DF410


Hi, I'm trying to configure DS125DF410 for 5.94Gb/s data rate I then calculated ppm count for 11.88Ghz and used divide by 2 in order to achieve a lock for the desired data rate.

After not receiving any signal on the other end I checked the status register (0x02) and everything seem to work properly except BIT[5] which equal 0.

Datasheet says as follow: "Signal quality and amplitude level is not sufficient for lock".

Can anyone help me understand what it means and what are the amplitude and signal quality required for lock according to datasheet.

Thank you

Daniel.

  • 0
    TI__Expert 8605 points

    Hello Daniel,

    Register 0x02[5] should equal 0. Are register 0x02 bits 3 and 4 equal to 1? These bits determine if the CDR is locked.

    For a 5.94 Gbps data rate please ensure that addresses 0x60 to 0x64 are set as follows:

     ADR0x60 = ADR0x62 = 0x66,   ADR0x61 = ADR0x63 = 0xBB

    Using the values above please follow the sequence shown below to configure the device for a 5.94 Gbps data rate.

    Please note register 0x2F must be set to 0xA6.

    Regards,

    Kia Rahbar

  • +1
    TI__Expert 8605 points

    Hello Daniel,

    Please note that I made some edits to the original post.

    Please make sure ADR0x60 = ADR0x62 = 0x66,   ADR0x61 = ADR0x63 = 0xBB, and ADR0x2F = 0xA6.

    Regards,

    Kia Rahbar

  • 0
    TI__Mastermind 19235 points

    Adding to Kia's response, the retimer signal detect assert thresholds are listed on the datasheet. See below for ease of reference. In order for its CDR to lock the retimer channel needs an input signal of data rate matching the programmed CDR rate (per channel register 0x2F or 0x60 - 0x63) and exceeding the signal detect thresholds. Note that these levels are specified at the device input i.e. after the input transmission media. 

    Thanks,

    Rodrigo

  • 0 in reply to Kia Rahbar
    Prodigy 20 points

    Thank you, I was missing ADR0x2F = 0xA6 after I added it I'm getting the signal on the other end sometimes for a short time but most of the time nothing come out on the other end.

    This is my initialization:

    //Reg           Val
//--------------------
  {0xFF,        0x0C}, // select ALL channels
  {0x00,        0x0F},  // Reset channel registers,self-clearing
  {0x36,        0x31},  // enable the 25 MHz reference clock
  {0x60,        0x66},  // Lower byte for 0x3B66 (PPM for 11.88Ghz clock for 5.94Gb/s data rate)
  {0x62,        0x66},
  {0x61,        0xBB},  // Upper byte for 0x3B66 + overide bit_7 (0x3B + 0x08 = 0xBB)
  {0x63,        0xBB},
  {0x64,        0xFF},  // Set tolerance to MAX (986 ppm for given clock rate) (more details in datasheet page 15)
  {0x2F,        0xA6},  // set divider ratio 2 for 11.88Ghz clock = 5.94Ghz
  {0x0A,        0x1C},  // reset the retimer CDR
  {0x0A,        0x10},

    I'm still getting BIT[7] = 0 for register 0x02 everything else is fine BIT[4] = 1 and BIT[3] =1 as expected. What could be the reason? unfortunately I don't have an access to a scope that can measure the signal in these frequencies.

  • 0 in reply to Daniel Ram
    Prodigy 20 points

    I managed to get it work thank you for the the help the problem was with the incoming signal.