TFP401: TFP401 ODCK and data phase confirm

Leon

Why do they need to know the phase difference? They need to make sure the setup/hold timing is met for ODCK and data as listed in the datasheet.

Thanks

David

我需要计算的input delay，需要知道odck和data之间的相位关系。

Hi,

The input clock to the TFP401 is conditioned by a phase-locked loop (PLL) to remove high-frequency jitter from the clock. The PLL also provides four 10× clock outputs of different phase to locate and sync the TMDS data streams (4× oversampling).

So the data output is always synchronized to the rising or falling edge of the output data clock, ODCK depends on the ODCK_INV setting.

Thanks

David 

Hi  David

Thanks for your reply .

Please refer to the diagram below

The details please check the customer descriptions below

BR,

Leon.liu

thanks leon，Tco和Tout，是2个重要的参数，data是通过ODCK来同步输出的话，经过一级寄存器，会有一个Tco和Tout的延时，就如上图所示。谢谢！