DS90UB934-Q1: MAP results

Which clocking mode is used on the SER?

Yes, this result looks okay!

Hi Hamzeh, 

Customer use PCLK from image sensor. Why all passing strobe on the right side?

Thanks,

Scarlett

Hi Hamzeh, 

Can we adapt strobe position in AEQ ?

The case is that customer got some return camera board from a mass production project. The problem is unstable lock between 933 and 934, resulting in cracked image. We think it might be problem due to not enough margin. Therefore customer uses MAP to help analyze.

Customer has also shared the PCLK jitter they measured on the return camera board with this issue and without. Could you help comment if this jitter is acceptable?

Thanks,

Scarlett

Hello Scarlett,

which Mode are you using, 10-bit or 12-bit ?

Also, we do not measure Cycle-Cycle jitter, but the Total Jitter @BER with Target BER = 10 (BER = 1E - 10). You need to measure using the filter settings shown in the datasheet "6.6 Recommended Serializer Timing For PCLK".

But generally what I can see in the measurements above, yes, this looks like high jitter.

Can they solder an external Osc on the Camera and test using the external CLK ?

Hi Hamzeh, 

Customer use 10-bit mode. I'm suggesting them try external Osc mode. 

Thanks,

Scarlett

Hi Scarlett,

For the PCLK they are using (84.7MHz) and 10-bit mode, the max allowed PCLK total jitter is 379ps

Can you also have them read the following registers in good and in error cases:

0x04, 0x05, 0x06, 0x36, 0x37, 0x41, 0x4C-0x4E, 0x51-0x58, 0x6D, 0x70-0x76, 0x7A, 0x7B, 0xD2-0xDB.