Hi support team,
I'm trying to implement SMBus master on FPGA to communicate with TUSB8042A.
Could you answer the following questions?
1. Is Read and Write protocol similar to the example of the following design guide?
SMBus Design Using MSP430
Design Guide
Figure 15. Write Word Protocol and Figure 16. Read Word Protocol
It's like
Write :
S SlaveAddr Wr A Reg A Data A P
Write :
S SlaveAddr Wr A Reg A S SlaveAddr Rd A Data A P
2. Does this device support Block Read and Block Write of SMBus Specification?
3. If the device support Block Read and Block Write, is it OK to over-write values on reserved address?
