TLK2711-SP: how to choose adequate clock ?

Random jitter rms needs to measured. You may do so for your oscillator in question via either the scope method or via phase noise measurement and subsequent integration using a spectrum analyzer. Once the sigma RJ value is obtained you would multiply it by the N factor for your desired BER level. Typically, low noise oscillators and frequency synthesizers such as does offered by TI will have RJ spec in the datasheet. See example below.

 https://www.ti.com/lit/ds/symlink/lmk61e2.pdf

Thanks,

Rodrigo Natal

Thanks a lot for your answer, I still have some question though.

On which integration band RJ should be measured ? The value will largerly depend on this integrated band.

Specially if the XO is direclty connected to the TLK (no filter, no PLL), shall the integration band be 1kHz to XXXX GHz ?

Plus, the measure of phase noise will be single side band.

Is the specification of RJ in single side band or double side band ? (folded noise)

For example, if RJ = 400 fs RMS -> how is it related to phase noise of the reference clock as the integration band is not given ?

Does it have to be divided by sqrt(2) to get non folded noise ?

Again, the goal is to choose a clock yet vendors often spec 12k-20MHz without noise folding.

Thanks

Audrey

In general, when RJ is measured via phase noise analysis we recommend to integrate from the CDR loop bandwidth to the Nyquist (i.e. baud rate/2) in frequency domain. The phase noise measurement is single side band. The random jitter value can also be checked in the time domain by using jitter decomposition via sampling scope measurement. Sampling scopes typically apply a histogram to the signal edge and the observed sigma value is the RJ. I'm not familiar with folder noise, but I don't think it comes into play here.

Thanks,

Rodrigo Natal

You may find the TI application note per the link below to be helpful.

https://www.ti.com/lit/an/scaa113/scaa113.pdf

Thanks for your answer,

How can I choose the start frequency of integration if there is no PLL ? CDR loop bandwidth won't be applicable.The rule is to take 1kHz ?

Then the stop frequency is Fclock /2 or baud rate/2 ? On TLK, maximum baud rate is at 2,5 Gbaud. Stop frequency would be 1,25 GHz ?

This means the integration band is very very large.

On TLK datasheet, it is specified : TX Budget = 80 ps peak-to-peak

Only a portion of the overall allowable transmit jitter is allocated to the reference clock ----->10%

So reference clock Jitter budget = 8 ps p-p

Rule of thumb => for modern clock generator, allocate 25% of allowable reference clock jitter to the deterministic and 75% to the random jitter.

Deterministic jitter = 25% total jitter = 2 ps p-p

Random jitter = 75% total jitter = 6 ps p-p

RJ = 6 ps / 14  (because DTD=0,5, BER =10^-12 ) = 0,428 ps RMS

So I have to choose a clock that presents 428 fs RMS jitter on 1kHz to 1,25 GHz integration band ?

There must be an error in the calculation.

Thank you

Audrey

Hi again,

My last point is that the jitter that comes from the TX Budget calculation must be double side-band ?

The part number CDC421A156 has a jitter as low as 380 fs RMS between 10kHz to 20 MHz in single side band ?

Thanks for your help!