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SN65LVDS94 skew requirement

Richard Dressman
Prodigy 20 points
Other Parts Discussed in Thread: SN65LVDS94, SN65LVDS93A

I've been trying to calculate the available system skew the sn65LVDS94 can tolerate based on the equation shown in the spec at the bottom of page 5. (trskm = tc/14 -ts/h). I am, however, confused with the ~2ns I get from the equation.

I had the impression that if I gate the tc = 35.56ns (Equal to a 28.18MHz event) that I would have ~2ns of available skew. This is based on the fact that 490ps of skew is budgeted as a minimum requirement. (From the spec).

I'm trying to get to a maximum available budget to allocate for my interface. Adding up SN65LVDS93A output skew, jitter, pair to pair differences and cable skew comes to some value. How can I calculate the margin I have between what you show in the spec and what my environment adds up to?

 

Ex:  SN65LVDS93A  1) tc +/- 100ps 2) Jitter = 42ps 3) LVDS Pair tolerance 65ps(based on 400mil differences in routing) 4) Cable skew of 40ps

Overall system skew of ~250ps

What will SN65LVDS94 tolerate?

Thanks.

  • 0
    TI__Mastermind 20985 points

    Hi Richard, I apologize for the delayed response.  I didn't receive an email notification for this message as I usually do; I think that technical problem is fixed for the future.

    I believe that the LVDS94 receiver input skew margin (tRSKM) is indeed about 2ns at 28.18MHz.  It's not clear to me where your confusion lies, since you said you calculated 2ns, and you had the impression you'd have 2ns (should one of those numbers be different?).

    Here's one way you can roughly estimate whether a calculated skew limit is reasonable.  Skew surely can't exceed 1 LVDS bit period, or even half that.  Half the bit period minus 500ps is an estimate of tRSKM.  35.56ns translates to 5.08ns bit periods, and a rough tRSKM estimate of 2.04ns.  By the numbers in the datasheet, I calculate tRSKM to be 1.8-2.2ns across -40 - +80C temperature.

    Skew is less of a concern at lower frequencies like 28MHz.  Also, you might not need to add the 42ps jitter in your skew calculation, since I'd expect the LVDS TX clock to be in lock-step with the data.

    Thanks,
    RE