DP83826I: Can't link to chip from PC

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>> Register readouts
>>
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Reg address 00 value = 3100 
Reg address 01 value = 7849 
Reg address 02 value = 2000 
Reg address 03 value = A130 
Reg address 04 value = 1E1 
Reg address 05 value = 0 
Reg address 06 value = 4 
Reg address 07 value = 2001 
Reg address 08 value = 0 
Reg address 09 value = 0 
Reg address 0A value = 100 
Reg address 0B value = 0 
Reg address 0C value = 0 
Reg address 0D value = 0 
Reg address 0E value = 0 
Reg address 0F value = 0 
Reg address 10 value = 2 
Reg address 11 value = 108 
Reg address 12 value = 0 
Reg address 13 value = 800 
Reg address 14 value = 0 
Reg address 15 value = 0 
Reg address 16 value = 100 
Reg address 17 value = 41 
Reg address 18 value = 400 
Reg address 19 value = C001 
Reg address 1A value = 0 
Reg address 1B value = 7D 
Reg address 1C value = 5EE 
Reg address 1D value = 0 
Reg address 1E value = 2 
Reg address 1F value = 0 
Reg address 25 value = 0 
Reg address 467 value = FFFF 
Reg address 468 value = FFFF 
Reg address 4D1 value = FFFF 


>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>>> STRAPPING REPORT
>>>
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
REG 0x00: 3100

Bit 13 Speed Selection RW, Strap 1 (CORRECT)
Speed Select:
1 = 100 Mbps
0 = 10 Mbps
When Auto-Negotiation is disabled (bit[12] = 0 in Register 0x0000),
writing to this bit allows the port speed to be selected.

bit 12 Auto-Negotiation Enable RW, Strap 1 (Correct)
Auto-Negotiation Enable:
1 = Enable Auto-Negotiation
0 = Disable Auto-Negotiation
If Auto-Negotiation is disabled, bit[8] and bit[13] of this register
determine the port speed and duplex mode


8 Duplex Mode RW, Strap 1 (CORRECT)
Duplex Mode:
1 = Full-Duplex
0 = Half-Duplex
When Auto-Negotiation is disabled, writing to this bit allows the port
Duplex capability to be selected.

REG 0x0A : 100

14 100Base-FX Enable RW, Strap 0 (CORRECT)
100Base-FX Enable:
1 = 100Base-FX mode enabled
0 = 100Base-FX mode disabled

REG 0x17 : 49

BIT 9 RGMII Mode RW, Strap 0 (CORRECT)
RGMII Mode Enable:
1 = Enable RGMII mode of operation
0 = Mode determined by bit[5]5 
->>>>>Bit 5 RMII Mode RW 0
RMII Mode Enable:
1 = Enable RMII mode of operation
0 = Enable MII mode of operation (MII Mode)

BIT 7 RMII Clock Select RW, Strap 0 (CORRECT)
RMII Reference Clock Select:
Strap XI_50 determines the clock reference requirement.
1 = 50-MHz clock reference, CMOS-level oscillator
0 = 25-MHz clock reference, crystal or CMOS-level oscillato


REG 0x18 : 400
TI says polarity WRONG!!!!! (Default Correct)

BIT 7 LED_0 Polarity RW, Strap 0
LED_0 Link Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
LED_0 polarity defined by strapping value of this pin. This register
allows for override of this strap value.

REG 0x19 : CC01

BIT 15 Auto MDI/X Enable RW, Strap 0 (NOT CORRECT == 1_
Auto-MDIX Enable:
1 = Enable Auto-Negotiation Auto-MDIX capability
0 = Disable Auto-Negotiation Auto-MDIX capability

BIT 5 LED Configuration RW, Strap 1 (NOT CORRECT == 0)
Configuration LED_CFG LED_0
1 1
ON for LINK
OFF for no LINK
2 0
ON for LINK
BLINK for TX/RX Activity

BIT 0:4 
4:0 PHY Address RO, Strap 0000 1 (CORRECT, Address is 1)
PHY Address:
Strapping configuration for PHY Address

REG 0x25 : 45E1

Bit 9 MLED Polarity Swap RW Strap Bit 9: 0) NOT SURE
MLED Polarity Swap: 
The polarity of MLED depends on the routing configuration and the
strap on COL pin. If the pin strap is Pull-Up then polarity is active low.
If the pin strap is Pull-Down then polarity is active high.

REG" 0x0467 : FFFF (DOES NOT MATCH - SEE Data sheet)

Table 83. 0x0467 Strap Latch-In Register #1 (SOR1) (continued)
BIT NAME TYPE DEFAULT FUNCTION
9:8 RX_ER Strap Mode RO, Strap 11 RX_ER Strap Mode:
Use same reference as defined by bits[15:14] in this register.
7:6 CRS Strap Mode RO, Strap 11 CRS Strap Mode:
Use same reference as defined by bits[15:14] in this register.
5:4 RX_DV Strap Mode RO, Strap 00 RX_DV Strap Mode:
Use same reference as defined by bits[15:14] in this register.
3:2 Reserved RO 00 Reserved
1:0 LED_0 Strap Mode RO, Strap 11
LED_0 Strap Mode:
00 = Mode 1
01 = Reserved
10 = Reserved
11 = Mode 4
Please refer to the strap section in the datasheet for information
regarding PHY configuration.
Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap
Mode and do not reflect the same bit sequence that is defined in the
strap section of the datasheet.

REG: 0x468 : FFFF  (NOT CORRECT)
3:2 RX_D3 Strap Mode RO, Strap 00 RX_D3 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467.
1:0 RX_D2 Strap Mode RO, Strap 00 RX_D2 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467

REG: 4D1 : FFFF (Not CORRECT)

0 EEE Capabilities Enable RW, Strap 0
EEE Capabilities Enable:
1 = PHY supports EEE capabilities
0 = PHY does not support EEE
When enabled, Auto-Negotiation will negotiate to EEE as defined by
register 0x003C and register 0x003D in MMD7.
When disabled, register 0x0014 in MMD3, register 0x003C and
register 0x003D in MMD7 are ignored.

// Full End to end Digital loopback (Note packet generator says its on and PHY enabled)
CR3 before= 0
CR3 reset stat = 0
CR3 after= 0
BISCR_Register before= 100
BISCR_Register after = 3304
BISCR2_Register packet length = 424
[15:8] at 0 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 5 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 10 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 15 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 20 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 25 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 30 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 35 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 40 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 45 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 50 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 55 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 60 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 65 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 70 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 75 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 80 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 85 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 90 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 95 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 100 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 105 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 110 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 115 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 120 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 125 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 130 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 135 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 140 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 145 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 150 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 155 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 160 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 165 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 170 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 175 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 180 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 185 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 190 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 195 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 200 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 205 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 210 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 215 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 220 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 225 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 230 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 235 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 240 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 245 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 250 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 255 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 260 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 265 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 270 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 275 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 280 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 285 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 290 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 295 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 300 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 305 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 310 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 315 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 320 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 325 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 330 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 335 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 340 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 345 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 350 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 355 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 360 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 365 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 370 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 375 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 380 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 385 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 390 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 395 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 400 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 405 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 410 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 415 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 420 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 425 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 430 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 435 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 440 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 445 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 450 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 455 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 460 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 465 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 470 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 475 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 480 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 485 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 490 secs is of the BICSR1 error count = 0
BISCR_Register = 3304
[15:8] at 495 secs is of the BICSR1 error count = 0
BISCR_Register = 3304




// MII Digital Loopback is requires following configuration:
//• 0x0000 = 0x2100 // Disable Auto-Neg
//• 0x0016 = 0x0104 // Digital Loopback
//• 0x0122 = 0x2000 /
//• 0x0123 = 0x2000
//• 0x0130 = 0x47FF
//• 0x001F = 0x4000 // Soft Rese

BISCR_Register before= 100
BISCR_Register after = 100
BISCR2_Register packet length = 5EE
CR3 before= 0
CR3 reset stat = 0
CR3 after= 0


[15:8] at 0 secs is of the BICSR1 error count = 0
[15:8] at 5 secs is of the BICSR1 error count = 0
[15:8] at 10 secs is of the BICSR1 error count = 0
[15:8] at 15 secs is of the BICSR1 error count = 0
[15:8] at 20 secs is of the BICSR1 error count = 0
[15:8] at 25 secs is of the BICSR1 error count = 0
[15:8] at 30 secs is of the BICSR1 error count = 0
[15:8] at 35 secs is of the BICSR1 error count = 0
[15:8] at 40 secs is of the BICSR1 error count = 0
[15:8] at 45 secs is of the BICSR1 error count = 0
[15:8] at 50 secs is of the BICSR1 error count = 0
[15:8] at 55 secs is of the BICSR1 error count = 0
[15:8] at 60 secs is of the BICSR1 error count = 0
[15:8] at 65 secs is of the BICSR1 error count = 0
[15:8] at 70 secs is of the BICSR1 error count = 0
[15:8] at 75 secs is of the BICSR1 error count = 0
[15:8] at 80 secs is of the BICSR1 error count = 0
[15:8] at 85 secs is of the BICSR1 error count = 0
[15:8] at 90 secs is of the BICSR1 error count = 0
[15:8] at 95 secs is of the BICSR1 error count = 0
[15:8] at 100 secs is of the BICSR1 error count = 0
[15:8] at 105 secs is of the BICSR1 error count = 0
[15:8] at 110 secs is of the BICSR1 error count = 0
[15:8] at 115 secs is of the BICSR1 error count = 0
[15:8] at 120 secs is of the BICSR1 error count = 0
[15:8] at 125 secs is of the BICSR1 error count = 0
[15:8] at 130 secs is of the BICSR1 error count = 0
[15:8] at 135 secs is of the BICSR1 error count = 0
[15:8] at 140 secs is of the BICSR1 error count = 0
[15:8] at 145 secs is of the BICSR1 error count = 0
[15:8] at 150 secs is of the BICSR1 error count = 0
[15:8] at 155 secs is of the BICSR1 error count = 0
[15:8] at 160 secs is of the BICSR1 error count = 0
[15:8] at 165 secs is of the BICSR1 error count = 0
[15:8] at 170 secs is of the BICSR1 error count = 0
[15:8] at 175 secs is of the BICSR1 error count = 0
[15:8] at 180 secs is of the BICSR1 error count = 0
[15:8] at 185 secs is of the BICSR1 error count = 0
[15:8] at 190 secs is of the BICSR1 error count = 0
[15:8] at 195 secs is of the BICSR1 error count = 0
[15:8] at 200 secs is of the BICSR1 error count = 0
[15:8] at 205 secs is of the BICSR1 error count = 0
[15:8] at 210 secs is of the BICSR1 error count = 0
[15:8] at 215 secs is of the BICSR1 error count = 0
[15:8] at 220 secs is of the BICSR1 error count = 0
[15:8] at 225 secs is of the BICSR1 error count = 0
[15:8] at 230 secs is of the BICSR1 error count = 0
[15:8] at 235 secs is of the BICSR1 error count = 0
[15:8] at 240 secs is of the BICSR1 error count = 0
[15:8] at 245 secs is of the BICSR1 error count = 0
[15:8] at 250 secs is of the BICSR1 error count = 0
[15:8] at 255 secs is of the BICSR1 error count = 0
[15:8] at 260 secs is of the BICSR1 error count = 0
[15:8] at 265 secs is of the BICSR1 error count = 0
[15:8] at 270 secs is of the BICSR1 error count = 0
[15:8] at 275 secs is of the BICSR1 error count = 0
[15:8] at 280 secs is of the BICSR1 error count = 0
[15:8] at 285 secs is of the BICSR1 error count = 0
[15:8] at 290 secs is of the BICSR1 error count = 0
[15:8] at 295 secs is of the BICSR1 error count = 0
[15:8] at 300 secs is of the BICSR1 error count = 0
[15:8] at 305 secs is of the BICSR1 error count = 0
[15:8] at 310 secs is of the BICSR1 error count = 0
[15:8] at 315 secs is of the BICSR1 error count = 0
[15:8] at 320 secs is of the BICSR1 error count = 0
[15:8] at 325 secs is of the BICSR1 error count = 0
[15:8] at 330 secs is of the BICSR1 error count = 0
[15:8] at 335 secs is of the BICSR1 error count = 0
[15:8] at 340 secs is of the BICSR1 error count = 0
[15:8] at 345 secs is of the BICSR1 error count = 0
[15:8] at 350 secs is of the BICSR1 error count = 0
[15:8] at 355 secs is of the BICSR1 error count = 0
[15:8] at 360 secs is of the BICSR1 error count = 0
[15:8] at 365 secs is of the BICSR1 error count = 0
[15:8] at 370 secs is of the BICSR1 error count = 0
[15:8] at 375 secs is of the BICSR1 error count = 0
[15:8] at 380 secs is of the BICSR1 error count = 0
[15:8] at 385 secs is of the BICSR1 error count = 0
[15:8] at 390 secs is of the BICSR1 error count = 0
[15:8] at 395 secs is of the BICSR1 error count = 0
[15:8] at 400 secs is of the BICSR1 error count = 0
[15:8] at 405 secs is of the BICSR1 error count = 0
[15:8] at 410 secs is of the BICSR1 error count = 0
[15:8] at 415 secs is of the BICSR1 error count = 0
[15:8] at 420 secs is of the BICSR1 error count = 0
[15:8] at 425 secs is of the BICSR1 error count = 0
[15:8] at 430 secs is of the BICSR1 error count = 0
[15:8] at 435 secs is of the BICSR1 error count = 0
[15:8] at 440 secs is of the BICSR1 error count = 0
[15:8] at 445 secs is of the BICSR1 error count = 0
[15:8] at 450 secs is of the BICSR1 error count = 0
[15:8] at 455 secs is of the BICSR1 error count = 0
[15:8] at 460 secs is of the BICSR1 error count = 0
[15:8] at 465 secs is of the BICSR1 error count = 0
[15:8] at 470 secs is of the BICSR1 error count = 0
[15:8] at 475 secs is of the BICSR1 error count = 0
[15:8] at 480 secs is of the BICSR1 error count = 0
[15:8] at 485 secs is of the BICSR1 error count = 0
[15:8] at 490 secs is of the BICSR1 error count = 0
[15:8] at 495 secs is of the BICSR1 error count = 0


>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Reverse Loopback

CR3 before= 0
CR3 reset stat = 0
CR3 after= 0
BISCR_Register before= 100
BISCR_Register after = 3310
BISCR2_Register packet length = 5EE
[15:8] at 0 secs is of the BICSR1 error count = 0
[15:8] at 5 secs is of the BICSR1 error count = 0
[15:8] at 10 secs is of the BICSR1 error count = 0
[15:8] at 15 secs is of the BICSR1 error count = 0
[15:8] at 20 secs is of the BICSR1 error count = 0
[15:8] at 25 secs is of the BICSR1 error count = 0
[15:8] at 30 secs is of the BICSR1 error count = 0
[15:8] at 35 secs is of the BICSR1 error count = 0
[15:8] at 40 secs is of the BICSR1 error count = 0
[15:8] at 45 secs is of the BICSR1 error count = 0
[15:8] at 50 secs is of the BICSR1 error count = 0
[15:8] at 55 secs is of the BICSR1 error count = 0
[15:8] at 60 secs is of the BICSR1 error count = 0
[15:8] at 65 secs is of the BICSR1 error count = 0
[15:8] at 70 secs is of the BICSR1 error count = 0
[15:8] at 75 secs is of the BICSR1 error count = 0
[15:8] at 80 secs is of the BICSR1 error count = 0
[15:8] at 85 secs is of the BICSR1 error count = 0
[15:8] at 90 secs is of the BICSR1 error count = 0
[15:8] at 95 secs is of the BICSR1 error count = 0
[15:8] at 100 secs is of the BICSR1 error count = 0
[15:8] at 105 secs is of the BICSR1 error count = 0
[15:8] at 110 secs is of the BICSR1 error count = 0
[15:8] at 115 secs is of the BICSR1 error count = 0
[15:8] at 120 secs is of the BICSR1 error count = 0
[15:8] at 125 secs is of the BICSR1 error count = 0
[15:8] at 130 secs is of the BICSR1 error count = 0
[15:8] at 135 secs is of the BICSR1 error count = 0
[15:8] at 140 secs is of the BICSR1 error count = 0
[15:8] at 145 secs is of the BICSR1 error count = 0
[15:8] at 150 secs is of the BICSR1 error count = 0
[15:8] at 155 secs is of the BICSR1 error count = 0
[15:8] at 160 secs is of the BICSR1 error count = 0
[15:8] at 165 secs is of the BICSR1 error count = 0
[15:8] at 170 secs is of the BICSR1 error count = 0
[15:8] at 175 secs is of the BICSR1 error count = 0
[15:8] at 180 secs is of the BICSR1 error count = 0
[15:8] at 185 secs is of the BICSR1 error count = 0
[15:8] at 190 secs is of the BICSR1 error count = 0
[15:8] at 195 secs is of the BICSR1 error count = 0
[15:8] at 200 secs is of the BICSR1 error count = 0
[15:8] at 205 secs is of the BICSR1 error count = 0
[15:8] at 210 secs is of the BICSR1 error count = 0
[15:8] at 215 secs is of the BICSR1 error count = 0
[15:8] at 220 secs is of the BICSR1 error count = 0
[15:8] at 225 secs is of the BICSR1 error count = 0
[15:8] at 230 secs is of the BICSR1 error count = 0
[15:8] at 235 secs is of the BICSR1 error count = 0
[15:8] at 240 secs is of the BICSR1 error count = 0
[15:8] at 245 secs is of the BICSR1 error count = 0
[15:8] at 250 secs is of the BICSR1 error count = 0
[15:8] at 255 secs is of the BICSR1 error count = 0
[15:8] at 260 secs is of the BICSR1 error count = 0
[15:8] at 265 secs is of the BICSR1 error count = 0
[15:8] at 270 secs is of the BICSR1 error count = 0
[15:8] at 275 secs is of the BICSR1 error count = 0
[15:8] at 280 secs is of the BICSR1 error count = 0
[15:8] at 285 secs is of the BICSR1 error count = 0
[15:8] at 290 secs is of the BICSR1 error count = 0
[15:8] at 295 secs is of the BICSR1 error count = 0
[15:8] at 300 secs is of the BICSR1 error count = 0
[15:8] at 305 secs is of the BICSR1 error count = 0
[15:8] at 310 secs is of the BICSR1 error count = 0
[15:8] at 315 secs is of the BICSR1 error count = 0
[15:8] at 320 secs is of the BICSR1 error count = 0
[15:8] at 325 secs is of the BICSR1 error count = 0
[15:8] at 330 secs is of the BICSR1 error count = 0
[15:8] at 335 secs is of the BICSR1 error count = 0
[15:8] at 340 secs is of the BICSR1 error count = 0
[15:8] at 345 secs is of the BICSR1 error count = 0
[15:8] at 350 secs is of the BICSR1 error count = 0
[15:8] at 355 secs is of the BICSR1 error count = 0
[15:8] at 360 secs is of the BICSR1 error count = 0
[15:8] at 365 secs is of the BICSR1 error count = 0
[15:8] at 370 secs is of the BICSR1 error count = 0
[15:8] at 375 secs is of the BICSR1 error count = 0
[15:8] at 380 secs is of the BICSR1 error count = 0
[15:8] at 385 secs is of the BICSR1 error count = 0
[15:8] at 390 secs is of the BICSR1 error count = 0
[15:8] at 395 secs is of the BICSR1 error count = 0
[15:8] at 400 secs is of the BICSR1 error count = 0
[15:8] at 405 secs is of the BICSR1 error count = 0
[15:8] at 410 secs is of the BICSR1 error count = 0
[15:8] at 415 secs is of the BICSR1 error count = 0
[15:8] at 420 secs is of the BICSR1 error count = 0
[15:8] at 425 secs is of the BICSR1 error count = 0
[15:8] at 430 secs is of the BICSR1 error count = 0
[15:8] at 435 secs is of the BICSR1 error count = 0
[15:8] at 440 secs is of the BICSR1 error count = 0
[15:8] at 445 secs is of the BICSR1 error count = 0
[15:8] at 450 secs is of the BICSR1 error count = 0
[15:8] at 455 secs is of the BICSR1 error count = 0
[15:8] at 460 secs is of the BICSR1 error count = 0
[15:8] at 465 secs is of the BICSR1 error count = 0
[15:8] at 470 secs is of the BICSR1 error count = 0
[15:8] at 475 secs is of the BICSR1 error count = 0
[15:8] at 480 secs is of the BICSR1 error count = 0
[15:8] at 485 secs is of the BICSR1 error count = 0
[15:8] at 490 secs is of the BICSR1 error count = 0
[15:8] at 495 secs is of the BICSR1 error count = 0

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Analog Loopback (Note:suggests 100 ohm termination which I don't have)

CR3 before= 0
CR3 reset stat = 0
CR3 after= 0
BISCR_Register before= 100
BISCR_Register after = 3308
BISCR2_Register packet length = 424
[15:8] at 0 secs is of the BICSR1 error count = 0
[15:8] at 5 secs is of the BICSR1 error count = 0
[15:8] at 10 secs is of the BICSR1 error count = 0
[15:8] at 15 secs is of the BICSR1 error count = 0
[15:8] at 20 secs is of the BICSR1 error count = 0
[15:8] at 25 secs is of the BICSR1 error count = 0
[15:8] at 30 secs is of the BICSR1 error count = 0
[15:8] at 35 secs is of the BICSR1 error count = 0
[15:8] at 40 secs is of the BICSR1 error count = 0
[15:8] at 45 secs is of the BICSR1 error count = 0
[15:8] at 50 secs is of the BICSR1 error count = 0
[15:8] at 55 secs is of the BICSR1 error count = 0
[15:8] at 60 secs is of the BICSR1 error count = 0
[15:8] at 65 secs is of the BICSR1 error count = 0
[15:8] at 70 secs is of the BICSR1 error count = 0
[15:8] at 75 secs is of the BICSR1 error count = 0
[15:8] at 80 secs is of the BICSR1 error count = 0
[15:8] at 85 secs is of the BICSR1 error count = 0
[15:8] at 90 secs is of the BICSR1 error count = 0
[15:8] at 95 secs is of the BICSR1 error count = 0
[15:8] at 100 secs is of the BICSR1 error count = 0
[15:8] at 105 secs is of the BICSR1 error count = 0
[15:8] at 110 secs is of the BICSR1 error count = 0
[15:8] at 115 secs is of the BICSR1 error count = 0
[15:8] at 120 secs is of the BICSR1 error count = 0
[15:8] at 125 secs is of the BICSR1 error count = 0
[15:8] at 130 secs is of the BICSR1 error count = 0
[15:8] at 135 secs is of the BICSR1 error count = 0
[15:8] at 140 secs is of the BICSR1 error count = 0
[15:8] at 145 secs is of the BICSR1 error count = 0
[15:8] at 150 secs is of the BICSR1 error count = 0
[15:8] at 155 secs is of the BICSR1 error count = 0
[15:8] at 160 secs is of the BICSR1 error count = 0
[15:8] at 165 secs is of the BICSR1 error count = 0
[15:8] at 170 secs is of the BICSR1 error count = 0
[15:8] at 175 secs is of the BICSR1 error count = 0
[15:8] at 180 secs is of the BICSR1 error count = 0
[15:8] at 185 secs is of the BICSR1 error count = 0
[15:8] at 190 secs is of the BICSR1 error count = 0
[15:8] at 195 secs is of the BICSR1 error count = 0
[15:8] at 200 secs is of the BICSR1 error count = 0
[15:8] at 205 secs is of the BICSR1 error count = 0
[15:8] at 210 secs is of the BICSR1 error count = 0
[15:8] at 215 secs is of the BICSR1 error count = 0
[15:8] at 220 secs is of the BICSR1 error count = 0
[15:8] at 225 secs is of the BICSR1 error count = 0
[15:8] at 230 secs is of the BICSR1 error count = 0
[15:8] at 235 secs is of the BICSR1 error count = 0
[15:8] at 240 secs is of the BICSR1 error count = 0
[15:8] at 245 secs is of the BICSR1 error count = 0
[15:8] at 250 secs is of the BICSR1 error count = 0
[15:8] at 255 secs is of the BICSR1 error count = 0
[15:8] at 260 secs is of the BICSR1 error count = 0
[15:8] at 265 secs is of the BICSR1 error count = 0
[15:8] at 270 secs is of the BICSR1 error count = 0
[15:8] at 275 secs is of the BICSR1 error count = 0
[15:8] at 280 secs is of the BICSR1 error count = 0
[15:8] at 285 secs is of the BICSR1 error count = 0
[15:8] at 290 secs is of the BICSR1 error count = 0
[15:8] at 295 secs is of the BICSR1 error count = 0
[15:8] at 300 secs is of the BICSR1 error count = 0
[15:8] at 305 secs is of the BICSR1 error count = 0
[15:8] at 310 secs is of the BICSR1 error count = 0
[15:8] at 315 secs is of the BICSR1 error count = 0
[15:8] at 320 secs is of the BICSR1 error count = 0
[15:8] at 325 secs is of the BICSR1 error count = 0
[15:8] at 330 secs is of the BICSR1 error count = 0
[15:8] at 335 secs is of the BICSR1 error count = 0
[15:8] at 340 secs is of the BICSR1 error count = 0
[15:8] at 345 secs is of the BICSR1 error count = 0
[15:8] at 350 secs is of the BICSR1 error count = 0
[15:8] at 355 secs is of the BICSR1 error count = 0
[15:8] at 360 secs is of the BICSR1 error count = 0
[15:8] at 365 secs is of the BICSR1 error count = 0
[15:8] at 370 secs is of the BICSR1 error count = 0
[15:8] at 375 secs is of the BICSR1 error count = 0
[15:8] at 380 secs is of the BICSR1 error count = 0
[15:8] at 385 secs is of the BICSR1 error count = 0
[15:8] at 390 secs is of the BICSR1 error count = 0
[15:8] at 395 secs is of the BICSR1 error count = 0
[15:8] at 400 secs is of the BICSR1 error count = 0
[15:8] at 405 secs is of the BICSR1 error count = 0
[15:8] at 410 secs is of the BICSR1 error count = 0
[15:8] at 415 secs is of the BICSR1 error count = 0
[15:8] at 420 secs is of the BICSR1 error count = 0
[15:8] at 425 secs is of the BICSR1 error count = 0
[15:8] at 430 secs is of the BICSR1 error count = 0
[15:8] at 435 secs is of the BICSR1 error count = 0
[15:8] at 440 secs is of the BICSR1 error count = 0
[15:8] at 445 secs is of the BICSR1 error count = 0
[15:8] at 450 secs is of the BICSR1 error count = 0
[15:8] at 455 secs is of the BICSR1 error count = 0
[15:8] at 460 secs is of the BICSR1 error count = 0
[15:8] at 465 secs is of the BICSR1 error count = 0
[15:8] at 470 secs is of the BICSR1 error count = 0
[15:8] at 475 secs is of the BICSR1 error count = 0
[15:8] at 480 secs is of the BICSR1 error count = 0
[15:8] at 485 secs is of the BICSR1 error count = 0
[15:8] at 490 secs is of the BICSR1 error count = 0
[15:8] at 495 secs is of the BICSR1 error count = 0

Using NPing to generate traffic. 8/17/22 9am.


From device: BISCR_Register = 3310



>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

Starting Nmap 7.92 ( https://nmap.org ) at 2022-08-17 07:54 Eastern Daylight Time

NSE: Loaded 155 scripts for scanning.

NSE: Script Pre-scanning.

Initiating NSE at 07:54

Completed NSE at 07:54, 0.00s elapsed

Initiating NSE at 07:54

Completed NSE at 07:54, 0.00s elapsed

Initiating NSE at 07:54

Completed NSE at 07:54, 0.00s elapsed

Initiating Ping Scan at 07:54

Scanning 192.168.0.5 [4 ports]

Completed Ping Scan at 07:54, 0.09s elapsed (1 total hosts)

Initiating Parallel DNS resolution of 1 host. at 07:54

Completed Parallel DNS resolution of 1 host. at 07:54, 0.32s elapsed

Initiating SYN Stealth Scan at 07:54

Scanning 192.168.0.5 [1000 ports]

Discovered open port 80/tcp on 192.168.0.5

Discovered open port 443/tcp on 192.168.0.5

Discovered open port 8008/tcp on 192.168.0.5

Discovered open port 8010/tcp on 192.168.0.5

Completed SYN Stealth Scan at 07:55, 5.88s elapsed (1000 total ports)

Initiating UDP Scan at 07:55

Scanning 192.168.0.5 [1000 ports]

Increasing send delay for 192.168.0.5 from 0 to 50 due to 11 out of 13 dropped probes since last increase.

Increasing send delay for 192.168.0.5 from 50 to 100 due to 11 out of 11 dropped probes since last increase.

UDP Scan Timing: About 6.88% done; ETC: 08:02 (0:07:00 remaining)

Increasing send delay for 192.168.0.5 from 100 to 200 due to 11 out of 11 dropped probes since last increase.

Increasing send delay for 192.168.0.5 from 200 to 400 due to max_successful_tryno increase to 5

UDP Scan Timing: About 7.79% done; ETC: 08:08 (0:12:02 remaining)

Increasing send delay for 192.168.0.5 from 400 to 800 due to max_successful_tryno increase to 6

Warning: 192.168.0.5 giving up on port because retransmission cap hit (6).

UDP Scan Timing: About 8.97% done; ETC: 08:11 (0:15:23 remaining)

UDP Scan Timing: About 9.54% done; ETC: 08:16 (0:19:07 remaining)

Increasing send delay for 192.168.0.5 from 800 to 1000 due to 11 out of 11 dropped probes since last increase.

UDP Scan Timing: About 10.27% done; ETC: 08:19 (0:21:59 remaining)

UDP Scan Timing: About 10.83% done; ETC: 08:22 (0:24:51 remaining)

UDP Scan Timing: About 11.49% done; ETC: 08:25 (0:27:06 remaining)

UDP Scan Timing: About 11.86% done; ETC: 08:28 (0:29:52 remaining)

UDP Scan Timing: About 12.50% done; ETC: 08:31 (0:31:37 remaining)

UDP Scan Timing: About 12.99% done; ETC: 08:33 (0:33:37 remaining)

UDP Scan Timing: About 13.50% done; ETC: 08:36 (0:35:40 remaining)

UDP Scan Timing: About 14.04% done; ETC: 08:38 (0:37:45 remaining)

UDP Scan Timing: About 15.00% done; ETC: 08:42 (0:40:03 remaining)

UDP Scan Timing: About 15.63% done; ETC: 08:45 (0:42:28 remaining)

UDP Scan Timing: About 17.37% done; ETC: 08:49 (0:45:02 remaining)

UDP Scan Timing: About 20.41% done; ETC: 08:55 (0:47:49 remaining)

UDP Scan Timing: About 45.26% done; ETC: 09:16 (0:44:43 remaining)

UDP Scan Timing: About 51.41% done; ETC: 09:18 (0:40:33 remaining)

UDP Scan Timing: About 57.39% done; ETC: 09:20 (0:36:20 remaining)

UDP Scan Timing: About 63.06% done; ETC: 09:21 (0:32:03 remaining)

UDP Scan Timing: About 68.51% done; ETC: 09:23 (0:27:43 remaining)

UDP Scan Timing: About 73.80% done; ETC: 09:24 (0:23:19 remaining)

UDP Scan Timing: About 79.10% done; ETC: 09:25 (0:18:51 remaining)

UDP Scan Timing: About 84.27% done; ETC: 09:26 (0:14:20 remaining)

UDP Scan Timing: About 89.41% done; ETC: 09:26 (0:09:43 remaining)

UDP Scan Timing: About 94.53% done; ETC: 09:28 (0:05:05 remaining)

UDP Scan Timing: About 99.07% done; ETC: 09:28 (0:00:52 remaining)