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Original question:

DS250DF810: When ds250df810 improves the 100g interface between switching chip and optical module, there are a lot of wrong...

DS250DF810: When adapting different optical modules, some 100g interface packets are wrong

sailchang
Prodigy 20 points
Part Number: DS250DF810

Hi

 interface is 100G，To eliminate the retimer Rx over-equalization problem，

1、We change the RX output emphasis control register in the optical module from 3dB to 0dB；

2、Forcing CTLE = 0x00 combined with limiting mode and reduced CTLE bias current

reg    value    mask

13      0x04    0x24

1a      0x00    0x08

2d      0x08    0x08

03      0x01     0xff

Rx adapt Mode set adapt-mode = 2;

Front-port ingress in 《DS250DF810_SNLU182_Programmers_Guide_confidential.pdf》 used for configuration reference;

When our equipment is connected with the customer's equipment, some modules are in use, and our receiving port is normal without wrong packets, but some modules are in use, and there are wrong packets that cannot be eliminated。The module is normally connected between other devices without wrong package.The wiring length from optical module to retimer Rx is between 0.8-4.2 inches，The board material is M6G；

It still feels like an over equalization problem！

Is there any other solution？

Is there any method to determine the adaptation parameters of retimer in our application scenario？

Thanks

  • 0
    TI__Mastermind 19225 points

    Hi,

    Related to: "When our equipment is connected with the customer's equipment, some modules are in use, and our receiving port is normal without wrong packets, but some modules are in use, and there are wrong packets that cannot be eliminated. The module is normally connected between other devices without wrong package. The wiring length from optical module to retimer Rx is between 0.8-4.2 inches. The board material is M6G"

    • To be able to debug this issue further it would be helpful for TI to obtain some system level register values for key retimer status parameters
    • Question: Could you provide a channel registers dump for both a good case with no packet errors as well as a problem case where wrong packets are being received. From the retimer side the following channel registers are of particular interest.
      • 0x02, 0x03, 0x27, 0x28, 0x31, 0x2F, 0x71, 0x72, 0x73, 0x74, 0x75, 0x78, 0x8F

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi

    We tested three kinds of optical modules (oak, OEM, Guanglian)；The opposite end is renix tester and litt880 device respectively.The same brand of optical modules are used at both ends every time.The data in the file is on retimer Rx.Channel 0-3 is a 100g port, and channel 4-7 is another 100g port。

    <retimerRxdevice-2-litt880-Optical_module-guanglian-noerror.txt>:This is the connection between the 100g port of the device and the litt880 device. Using the Guanglian optical module, there is no wrong package in the test;

    ds250df810testdata.zip

    Thanks

  • 0 in reply to sailchang
    TI__Mastermind 19225 points

    Thank you for sharing your system level retimer log files. I do seen that the problem channels show lower than ideal input eye opening values. Below are my debug suggestions.

    • I see that channel register 0x31 is set to 0x40 for adapt mode 2 (CTLE + DFE adaptation) but the DFE has not been enabled via channel register write
      • For all DFE taps to be active they must be enabled by setting channel register 0x1E=0xE3
      • if using the DFE the limiting mode should be disabled by setting channel register 0x13[2]=0
    • It's possible that the signal amplitude from the optical module electrical output is low. For such cases the user may enable the retimer VGA by setting 0x8E[0]=1

    Regards,

    Rodrigo Natal